plf_spce3200.h

ecos下的gui开发源代码

#ifndef CYGONCE_HAL_PLF_SPCE3200_H
#define CYGONCE_HAL_PLF_SPCE3200_H
//=============================================================================
//
//      plf_spce3200.h
//
//      Platform header for hardware resource map.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   lijian
// Contributors:lijian
// Date:        2007-11-26
// Purpose:     Platform For Spce3200 hareware resource mapping definition.
// Usage:       #include <cyg/hal/plf_spce3200.h>
//              
//####DESCRIPTIONEND####
//
//=============================================================================
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>

//******************************************************************//
//                           Constant                               //
//******************************************************************//
typedef volatile unsigned int UV32;

//**************************************************************//
//                        CKG & PLL                             //
//**************************************************************//
#define P_CLK_CPU_SEL                       (UV32*)0x88210004
#define P_CLK_AHB_CONF                      (UV32*)0x88210008
#define P_CLK_AHB_SEL                       (UV32*)0x8821000C
#define P_CLK_PLLV_CONF                     (UV32*)0x882100B4
#define P_CLK_PLLV_SEL                      (UV32*)0x882100B8
#define P_CLK_PLLAU_CONF                    (UV32*)0x882100bc
#define P_CLK_32K_CONF                      (UV32*)0x88210114
#define P_PLLV_STABLE_TIME                  (UV32*)0x88210104
#define P_BUFCTRL_CLK_CONF                  (UV32*)0x882100C8
//**************************************************************//
//                           GPIO                               //
//**************************************************************//
#define P_GPIO_CLK_CONF                     (UV32*)0x882100FC
#define P_IOA_GPIO_SETUP                    (UV32*)0x88200038
#define P_IOB_GPIO_SETUP                    (UV32*)0x8820004C
#define P_IOB_GPIO_INPUT                    (UV32*)0x88200070
#define P_IOA_GPIO_INPUT                    (UV32*)0x88200074
#define P_IOA_GPIO_INT                      (UV32*)0x88200090
//**************************************************************//
//                           SFTCFG                             //
//**************************************************************//
#define P_ROMCSN_INTERFACE_SEL              (UV32*)0x88200004
#define P_DRAM_INTERFACE_SEL                (UV32*)0x88200008
#define P_DRAM_GPIO_SETUP                   (UV32*)0x88200050
#define P_DRAM_GPIO_INPUT                   (UV32*)0x88200070
#define P_CLK_CPU2MPEG4_SEL                 (UV32*)0x882000C0
//**************************************************************//
//                            WDOG                              //
//**************************************************************//
#define P_WDOG_CLK_CONF                     (UV32*)0x88210084
#define P_WDOG_RESET_STATUS                 (UV32*)0x882100E8
#define P_WDOG_MODE_CTRL                    (UV32*)0x88170000
#define P_WDOG_CYCLE_SETUP                  (UV32*)0x88170004
#define P_WDOG_CLR_COMMAND                  (UV32*)0x88170008
//**************************************************************//
//                          Sleep-Wakeup                        //
//**************************************************************//
#define P_SLEEP_MODE_CTRL                   (UV32*)0x88210000
#define P_SLEEP_CLK_SEL                     (UV32*)0x882100DC
#define P_WAKEUP_KEYC_SEL                   (UV32*)0x88200008
#define P_WAKEUP_KEYC_CLR                   (UV32*)0x882100C0
//**************************************************************//
//                            INT                               //
//**************************************************************//
#define P_INT_CLK_CONF                      (UV32*)0x882100D0
#define P_INT_REQ_STATUS1                   (UV32*)0x880a0000
#define P_INT_REQ_STATUS2                   (UV32*)0x880a0004
#define P_INT_GROUP_PRI                     (UV32*)0x880a0008
#define P_INT_GROUP0_PRI                    (UV32*)0x880a0010
#define P_INT_GROUP1_PRI                    (UV32*)0x880a0014
#define P_INT_GROUP2_PRI                    (UV32*)0x880a0018
#define P_INT_GROUP3_PRI                    (UV32*)0x880a001C
#define P_INT_MASK_CTRL1                    (UV32*)0x880a0020
#define P_INT_MASK_CTRL2                    (UV32*)0x880a0024
//**************************************************************//
//                              MIU                             //
//**************************************************************//
#define P_MIU_CLK_CONF                      (UV32*)0x88210010
#define P_MIU_SDRAM_POWER                   (UV32*)0x8807005C
#define P_MIU_SDRAM_SETUP1                  (UV32*)0x88070060
#define P_MIU_SDRAM_SETUP2                  (UV32*)0x88070094
#define P_MIU_SDRAM_SETUP3                  (UV32*)0x88230060
#define P_MIU_SDRAM_STATUS                  (UV32*)0x8807006C
//**************************************************************//
//                            APBDMA                            //
//**************************************************************//
#define P_DMA_CLK_CONF                      (UV32*)0x88210058
#define P_DMA_BUSY_STATUS                   (UV32*)0x88080000
#define P_DMA_INT_STATUS                    (UV32*)0x88080004
#define P_DMA_AHB_SA0BA                     (UV32*)0x88080008
#define P_DMA_AHB_SA1BA                     (UV32*)0x8808000C
#define P_DMA_AHB_SA2BA                     (UV32*)0x88080010
#define P_DMA_AHB_SA3BA                     (UV32*)0x88080014
#define P_DMA_AHB_EA0BA                     (UV32*)0x88080018
#define P_DMA_AHB_EA1BA                     (UV32*)0x8808001C
#define P_DMA_AHB_EA2BA                     (UV32*)0x88080020
#define P_DMA_AHB_EA3BA                     (UV32*)0x88080024
#define P_DMA_APB_SA0                       (UV32*)0x88080028
#define P_DMA_APB_SA1                       (UV32*)0x8808002C
#define P_DMA_APB_SA2                       (UV32*)0x88080030
#define P_DMA_APB_SA3                       (UV32*)0x88080034
#define P_DMA_AHB_SA0BB                     (UV32*)0x8808004C
#define P_DMA_AHB_SA1BB                     (UV32*)0x88080050
#define P_DMA_AHB_SA2BB                     (UV32*)0x88080054
#define P_DMA_AHB_SA3BB                     (UV32*)0x88080058
#define P_DMA_AHB_EA0BB                     (UV32*)0x8808005C
#define P_DMA_AHB_EA1BB                     (UV32*)0x88080060
#define P_DMA_AHB_EA2BB                     (UV32*)0x88080064
#define P_DMA_AHB_EA3BB                     (UV32*)0x88080068
#define P_DMA_CHANNEL0_CTRL                 (UV32*)0x8808006C
#define P_DMA_CHANNEL1_CTRL                 (UV32*)0x88080070
#define P_DMA_CHANNEL2_CTRL                 (UV32*)0x88080074
#define P_DMA_CHANNEL3_CTRL                 (UV32*)0x88080078
#define P_DMA_CHANNEL_RESET                 (UV32*)0x8808007C
//**************************************************************//
//                           ADC                                //
//**************************************************************//
#define P_ADC_CLK_CONF                      (UV32*)0x882100AC
#define P_ADC_CLK_SEL                       (UV32*)0x882100B0
#define P_ADC_GPIO_SETUP                    (UV32*)0x88200048
#define P_ADC_GPIO_INPUT                    (UV32*)0x88200078
#define P_ADC_GPIO_INT                      (UV32*)0x8820009C
#define P_ADC_AINPUT_CTRL                   (UV32*)0x88200054
#define P_ADC_MIC_CTRL1                     (UV32*)0x881a0000
#define P_ADC_MIC_GAIN                      (UV32*)0x881a0004
#define P_ADC_SAMPLE_CLK                    (UV32*)0x881a0008
#define P_ADC_SAMPLE_HOLD                   (UV32*)0x881a000c
#define P_ADC_MIC_CTRL2                     (UV32*)0x881a0010
#define P_ADC_INT_STATUS                    (UV32*)0x881a0014
#define P_ADC_MANUAL_DATA                   (UV32*)0x881a0018
#define P_ADC_AUTO_DATA                     (UV32*)0x881a001c
#define P_ADC_MIC_DATA                      (UV32*)0x881a0020
//**************************************************************//
//                           DAC                                //
//**************************************************************//
#define P_DAC_CLK_CONF                      (UV32*)0x8821003C
#define P_DAC_FIFOBA_LOW                    (UV32*)0x88051080
#define P_DAC_FIFOBA_HIGH                   (UV32*)0x88051084
#define P_DAC_SAMPLE_CLK                    (UV32*)0x88051064
#define P_DAC_INT_STATUS                    (UV32*)0x88051088
#define P_DAC_MODE_CTRL1                    (UV32*)0x88051474
#define P_DAC_MODE_CTRL2                    (UV32*)0x88051034
#define P_DAC_OUTPUT_CH0                    (UV32*)0x88051040
#define P_DAC_OUTPUT_CH1                    (UV32*)0x88051044
//**************************************************************//
//                              Timer                           //
//**************************************************************//
#define P_TIMER_CLK_SEL                     (UV32*)0x882100E4
#define P_TIMER_INTERFACE_SEL               (UV32*)0x88200010
#define P_TIMER0_CLK_CONF                   (UV32*)0x8821006C
#define P_TIMER0_MODE_CTRL                  (UV32*)0x88160000
#define P_TIMER0_CCP_CTRL                   (UV32*)0x88160004
#define P_TIMER0_PRELOAD_DATA               (UV32*)0x88160008
#define P_TIMER0_CCP_DATA                   (UV32*)0x8816000C
#define P_TIMER0_COUNT_DATA                 (UV32*)0x88160010
#define P_TIMER1_CLK_CONF                   (UV32*)0x88210070
#define P_TIMER1_MODE_CTRL                  (UV32*)0x88161000
#define P_TIMER1_CCP_CTRL                   (UV32*)0x88161004
#define P_TIMER1_PRELOAD_DATA               (UV32*)0x88161008
#define P_TIMER1_CCP_DATA                   (UV32*)0x8816100C
#define P_TIMER1_COUNT_DATA                 (UV32*)0x88161010
#define P_TIMER2_CLK_CONF                   (UV32*)0x88210074
#define P_TIMER2_MODE_CTRL                  (UV32*)0x88162000
#define P_TIMER2_CCP_CTRL                   (UV32*)0x88162004
#define P_TIMER2_PRELOAD_DATA               (UV32*)0x88162008
#define P_TIMER2_CCP_DATA                   (UV32*)0x8816200C
#define P_TIMER2_COUNT_DATA                 (UV32*)0x88162010
#define P_TIMER3_CLK_CONF                   (UV32*)0x88210078
#define P_TIMER3_MODE_CTRL                  (UV32*)0x88163000
#define P_TIMER3_CCP_CTRL                   (UV32*)0x88163004
#define P_TIMER3_PRELOAD_DATA               (UV32*)0x88163008
#define P_TIMER3_CCP_DATA                   (UV32*)0x8816300C
#define P_TIMER3_COUNT_DATA                 (UV32*)0x88163010
#define P_TIMER4_CLK_CONF                   (UV32*)0x8821007C
#define P_TIMER4_MODE_CTRL                  (UV32*)0x88164000