hal_cache.h

ecos下的gui开发源代码

                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_DCACHE_LOCK_DEFINED
#endif

// Undo a previous lock operation.
// Do this by flushing the cache, which is defined to clear the lock bit.
#ifndef HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _asize_)									  \
    CYG_MACRO_START                                                           \
    cyg_uint32 __base = (cyg_uint32)(HAL_DCACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_DCACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_DCACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
					  "cache 0xD, [r8,0];"                                    \
					  "nop;nop;nop;nop;nop;"                                  \
                      "cache 0xA, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop"                                           \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_DCACHE_UNLOCK_DEFINED
#endif

// Unlock entire cache
#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL()				\
		HAL_DCACHE_SYNC()					\
        HAL_DCACHE_INVALIDATE_ALL()

#define HAL_DCACHE_UNLOCK_ALL_DEFINED
#endif

//-----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
// This uses the hit-writeback-invalidate cache operation.
#ifndef HAL_DCACHE_FLUSH_DEFINED
#define HAL_DCACHE_FLUSH( _base_ , _asize_ )                                  \
    CYG_MACRO_START                                                           \
    cyg_uint32 __base = (cyg_uint32)(HAL_DCACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_DCACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_DCACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0xE, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop;"                                           \
   		  			  "cache  0x1a,[r8,0];nop;"								  \
			          "nop; nop; nop; nop;"									  \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_DCACHE_FLUSH_DEFINED
#endif

// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ )                             \
    CYG_MACRO_START                                                           \
    cyg_uint32 __base = (cyg_uint32)(HAL_DCACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_DCACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_DCACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0xA, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop"                                           \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_DCACHE_INVALIDATE_DEFINED
#endif

// Write dirty cache lines to memory for the given address range.
// This uses the hit-writeback cache operation.
#ifndef HAL_DCACHE_STORE_DEFINED
#define HAL_DCACHE_STORE( _base_ , _asize_ )                                  \
    CYG_MACRO_START                                                           \
	cyg_uint32 __base = (cyg_uint32)(HAL_DCACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_DCACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_DCACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0xD, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop;"                                           \
					  "cache  0x1a,[r8,0];nop;"								  \
			          "nop; nop; nop; nop;"									  \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_DCACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_DCACHE_STORE_DEFINED
#endif

// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )

// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )

// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )

//-----------------------------------------------------------------------------
// Global control of Instruction cache

// Enable the instruction cache
// There is no default mechanism for enabling or disabling the caches.
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE()							\
    CYG_MACRO_START                                 \
       	  asm volatile (						    \
			"nop;nop;nop;"	/*ICACHE is always*/	\
			"nop;nop;"		/*enable */             \
			);										\
    CYG_MACRO_END

#define HAL_ICACHE_ENABLE_DEFINED
#endif

// Disable the instruction cache
//Score cannot disable Icache 
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE()

#define HAL_ICACHE_DISABLE_DEFINED
#endif

#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;

#define HAL_ICACHE_IS_ENABLED_DEFINED
#endif

// Invalidate the entire cache
// This uses the index-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL()									\
    CYG_MACRO_START													\
       	  asm volatile (											\
			"la	r8, cyg_start;"										\
			"cache 0x10,[r8,0]; nop; nop; nop; nop; nop;"			\
			:														\
			:														\
			:"r8" 													\
			);														\
    CYG_MACRO_END

#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#endif

// Synchronize the contents of the cache with memory.
// Simply force the cache to reload.
#ifndef HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()

#define HAL_ICACHE_SYNC_DEFINED
#endif

// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)

// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_)                                      \
    CYG_MACRO_START                                                           \
	cyg_uint32 __base = (cyg_uint32)(HAL_ICACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_ICACHE_END_ADDRESS(_base_,_asize_)-__base) / HAL_ICACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0x1, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop"                                           \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_ICACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \
    CYG_MACRO_END

#define HAL_ICACHE_LOCK_DEFINED
#endif

// Undo a previous lock operation.
// Do this by invalidating the cache, which is defined to clear the lock bit.
#ifndef HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _size_)									  \
	cyg_uint32 __base = (cyg_uint32)(HAL_ICACHE_START_ADDRESS(_base_));       \
    cyg_int32 __count = ((HAL_ICACHE_END_ADDRESS(_base_,_size_)-__base) / HAL_ICACHE_LINE_SIZE);                   \
    do {                                                                      \
        asm volatile ("mv   r8,%0;"	                                          \
                      "cache 0x2, [r8,0];"                                    \
                      "nop;nop;"		                                      \
                      "nop;nop;nop"                                           \
                      :							                              \
                      : /* %0 */ "r" (__base)                                 \
                      :"r8");												  \
        __base += HAL_ICACHE_LINE_SIZE;                                       \
    } while (__count--);                                                      \

#define HAL_ICACHE_UNLOCK_DEFINED
#endif

// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()

//-----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                           \
    CYG_MACRO_START                                                         \
	HAL_ICACHE_UNLOCK(_base_, _asize_);                                      \
    CYG_MACRO_END

#define HAL_ICACHE_INVALIDATE_DEFINED
#endif

//-----------------------------------------------------------------------------
// Check that a supported configuration has actually defined some macros.

#ifndef HAL_DCACHE_ENABLE

#error Unsupported Score configuration

#endif

//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h