page_0.h

以ST公司CPU为核心的彩色电视机的完整源程序。

#ifndef _PAGE_0
#define _PAGE_0

/****************************************************************************************/
/*      Page 0:                                                                         */
/*      External interrupts, Timer Watchdog, SPI control registers  release 4.0         */
/*              External interrupt control register                                     */
/*                                                                                      */
/****************************************************************************************/

#define EXINT_PG ((unsigned char)0 )                    /* EXTERNAL interrupt register page */

register volatile unsigned char EITR asm("R242");       /* External interrupt trigger level register */

#define EIm_tea0m ((unsigned char)0x01)                 /* Trigger Event A0 mask */
#define EIm_tea1m ((unsigned char)0x02)                 /* Trigger Event A1 mask */
#define EIm_teb0m ((unsigned char)0x04)                 /* Trigger Event B0 mask */
#define EIm_teb1m ((unsigned char)0x08)                 /* Trigger Event B1 mask */
#define EIm_tec0m ((unsigned char)0x10)                 /* Trigger Event C0 mask */
#define EIm_tec1m ((unsigned char)0x20)                 /* Trigger Event C1 mask */
#define EIm_ted0m ((unsigned char)0x40)                 /* Trigger Event D0 mask */
#define EIm_ted1m ((unsigned char)0x80)                 /* Trigger Event D1 mask */

register volatile unsigned char EIPR asm("R243");       /* External interrupt pending register */
 
#define EIm_ipa0m ((unsigned char)0x01)                 /* Interrupt Pending A0 mask */
#define EIm_ipa1m ((unsigned char)0x02)                 /* Interrupt Pending A1 mask */
#define EIm_ipb0m ((unsigned char)0x04)                 /* Interrupt Pending B0 mask */
#define EIm_ipb1m ((unsigned char)0x08)                 /* Interrupt Pending B1 mask */
#define EIm_ipc0m ((unsigned char)0x10)                 /* Interrupt Pending C0 mask */
#define EIm_ipc1m ((unsigned char)0x20)                 /* Interrupt Pending C1 mask */
#define EIm_ipd0m ((unsigned char)0x40)                 /* Interrupt Pending D0 mask */
#define EIm_ipd1m ((unsigned char)0x80)                 /* Interrupt Pending D1 mask */

register volatile unsigned char EIMR asm("R244");       /* External interrupt mask register */

#define EIm_ia0m ((unsigned char)0x01)                  /* Int. A0 mask */
#define EIm_ia1m ((unsigned char)0x02)                  /* Int. A1 mask */
#define EIm_ib0m ((unsigned char)0x04)                  /* Int. B0 mask */
#define EIm_ib1m ((unsigned char)0x08)                  /* Int. B1 mask */
#define EIm_ic0m ((unsigned char)0x10)                  /* Int. C0 mask */
#define EIm_ic1m ((unsigned char)0x20)                  /* Int. C1 mask */
#define EIm_id0m ((unsigned char)0x40)                  /* Int. D0 mask */
#define EIm_id1m ((unsigned char)0x80)                  /* Int. D1 mask */


register volatile unsigned char EIPLR asm("R245");      /* Ext. interrupt priority level register */

register volatile unsigned char EIVR asm("R246");       /* External interrupt vector register */

#define EIm_ewenm  ((unsigned char)0x01)                /* External wait enable mask */
#define EIm_iaosm  ((unsigned char)0x02)                /* Interrupt A0 selection mask */
#define EIm_tlism  ((unsigned char)0x04)                /* Top level Input selection mask */
#define EIm_tltevm ((unsigned char)0x08)                /* Top level trigger event mask */

register volatile unsigned char NICR asm("R247");       /* Nested interrupt control register */

#define EIm_tlnmm ((unsigned char)0x80)                 /* Top level not maskable mask */


/****************************************/
/* Timer Watchdog control registers     */
/****************************************/

#define WDT_PG ((unsigned char)0 )                      /* Timer Watchdog page */

register volatile unsigned int  WDTR asm("RR248");      /* TWD timer constant register. */

register volatile unsigned char WDTHR asm("R248");      /* TWD timer high constant register */

register volatile unsigned char WDTLR asm("R249");      /* TWD timer low constant register */

register volatile unsigned char WDTPR asm("R250");      /* TWD timer prescaler constant register */

register volatile unsigned char WDTCR asm("R251");      /* TWD timer control register */

#define WDTm_stsp    ((unsigned char)0x80)              /* TWD start stop mask */
#define WDTm_sc      ((unsigned char)0x40)              /* TWD single continuous mode mask */
#define WDTm_inen    ((unsigned char)0x08)              /* TWD input section enable/disable mask */
#define WDTm_outmd   ((unsigned char)0x04)              /* TWD output mode mask */
#define WDTm_wrout   ((unsigned char)0x02)              /* TWD output bit mask */
#define WDTm_outen   ((unsigned char)0x01)              /* TWD output enable mask */

#define WDTm_inm_evc ((unsigned char)0x00)              /* TWD input mode event counter. */
#define WDTm_inm_g   ((unsigned char)0x10)              /* TWD input mode gated. */
#define WDTm_inm_t   ((unsigned char)0x20)              /* TWD input mode triggerable. */
#define WDTm_inm_rt  ((unsigned char)0x30)              /* TWD input mode retriggerable. */


/******************************/
/* Wait control registers     */
/******************************/

register volatile unsigned char WCR asm("R252");        /* Wait control register */

#define Wm_wdgen ((unsigned char)0x40)                  /* TWD timer enable mask */
#define Wm_wdm2  ((unsigned char)0x20)                  /* Data Memory Wait Cycle */
#define Wm_wdm1  ((unsigned char)0x10)                  /* Data Memory Wait Cycle */ 
#define Wm_wdm0  ((unsigned char)0x08)                  /* Data Memory Wait Cycle */
#define Wm_wpm2  ((unsigned char)0x04)                  /* Program Memory Wait Cycle  */
#define Wm_wpm1  ((unsigned char)02)                    /* Program Memory Wait Cycle  */
#define Wm_wpm0  ((unsigned char)01)                    /* Program Memory Wait Cycle  */

#define Wm_dmwc1  Wm_wdm0                               /* 1 wait cycle  on Data M. */
#define Wm_dmwc2  Wm_wdm1                               /* 2 wait cycles on Data M. */
#define Wm_dmwc3 (Wm_wdm1 | Wm_wdm0)                    /* 3 wait cycles on Data M. */
#define Wm_dmwc4  Wm_wdm2                               /* 4 wait cycles on Data M. */
#define Wm_dmwc5 (Wm_wdm2 | Wm_wdm0)                    /* 5 wait cycles on Data M. */
#define Wm_dmwc6 (Wm_wdm2 | Wm_wdm1)                    /* 6 wait cycles on Data M. */
#define Wm_dmwc7 (Wm_wdm2 | Wm_wdm1 | Wm_wdm0)          /* 7 wait cycles on Data M. */

#define Wm_pmwc1  Wm_wpm0                               /* 1 wait cycle  on Prog M. */
#define Wm_pmwc2  Wm_wpm1                               /* 2 wait cycles on Prog M. */
#define Wm_pmwc3 (Wm_wpm1 | Wm_wpm0 )                   /* 3 wait cycles on Prog M. */
#define Wm_pmwc4  Wm_wpm2                               /* 4 wait cycles on Prog M. */
#define Wm_pmwc5 (Wm_wpm2 | Wm_wpm0 )                   /* 5 wait cycles on Prog M. */
#define Wm_pmwc6 (Wm_wpm2 | Wm_wpm1 )                   /* 6 wait cycles on Prog M. */
#define Wm_pmwc7 (Wm_wpm2 | Wm_wpm1 | Wm_wpm0)          /* 7 wait cycles on Prog M. */


/********************************/
/* SPI control registers        */
/********************************/

#define SPI_PG ((unsigned char)0 )                      /* SPI register page */

register volatile unsigned char SPIDR asm("R253");      /* SPI Data register */

register volatile unsigned char SPICR asm("R254");      /* SPI Control register */

#define SPm_spen    ((unsigned char)0x80)               /* Serial Peripheral Enable mask */
#define SPm_bms     ((unsigned char)0x40)               /* SBUS/I2C bus selector mask */
#define SPm_arb     ((unsigned char)0x20)               /* Arbitration mask */
#define SPm_sp_busy ((unsigned char)0x10)               /* SPI busy mask */
#define SPm_cpol    ((unsigned char)0x08)               /* SPI transmission clock polarity mask */
#define SPm_cpha    ((unsigned char)0x04)               /* SPI transmission clock phase */

#define SPm_8       ((unsigned char)0x00)               /* SPI clock divider   8 = 1500 kHz (12MHz) */
#define SPm_16      ((unsigned char)0x01)               /* SPI clock divider  16 =  750 kHz (12MHz) */
#define SPm_128     ((unsigned char)0x02)               /* SPI clock divider 128 = 93.75 kHz (12MHz) */
#define SPm_256     ((unsigned char)0x03)               /* SPI clock divider 256 = 46.87 kHz (12MHz) */


#endif