📄 i2c_bus.c
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/****************************************************************************
FILENAME : I2C_BUS.C
VERSION : V1.0
DATE : JAN 1999
AUTHOR(s) : VICK ZHONG
PROCESSOR : ST92195
DESCRIPTION : This file contains the access functions for the I2C bus.
MODIFICATIONS:
-
*****************************************************************************/
#include "st92196.h"
#include "macro.h"
#include "tv_glob.h"
#include "register.h"
#include "utility.h"
#include "video.h"
#include "autosrch.h"
#include "timer.h"
#include "i2c_bus.h"
unsigned char read_data[4];
/* initilize the i2c bus */
/******************************************************************************
FUNCTION : InitI2cBus
INPUTS : attr - the value may set into I2CFQR register
OUTPUTS : %
DESCRIPTION : This function initialzes the i2c-bus work status.
*****************************************************************************/
void InitI2cBus (unsigned char attr)
{
switch (attr & I2C_CHANNEL_MASK)
{
case 0x00: /* P24 & 25 used */
spp (P2C_PG); /* set page pointer to I/O registers page */
P2C0R |= 0x30; /* set bits 4&5 of P2 control register 0 */
P2C1R |= 0x30; /* set bits 4&5 of P2 control register 1 */
P2C2R |= 0x30; /* set bits 4&5 of P2 control register 2 */
/* P24&P25 configure as AF out / OD / TTL */
break;
case 0x80: /* P34 & 35 used */
spp (P3C_PG); /* set page pointer to I/O registers page */
P3C0R |= 0x30; /* set bits 4&5 of P3 control register 0 */
P3C1R |= 0x30; /* set bits 4&5 of P3 control register 1 */
P3C2R |= 0x30; /* set bits 4&5 of P3 control register 2 */
/* P34&P35 configure as AF out / OD / TTL */
break;
case 0x40: /* P30 & P31 used */
spp (P3C_PG); /* set page pointer to I/O registers page */
P3C0R |= 0x03; /* set bits 0&1 of P3 control register 0 */
P3C1R |= 0x03; /* set bits 0&1 of P3 control register 1 */
P3C2R |= 0x03; /* set bits 0&1 of P3 control register 2 */
/* P30&P31 configure as AF out / OD / TTL */
break;
case 0xC0: /* P40 & P41 used */
spp (P4C_PG); /* set page pointer to I/O registers page */
P4C0R |= 0x03; /* set bits 0&1 of P3 control register 0 */
P4C1R |= 0x03; /* set bits 0&1 of P3 control register 1 */
P4C2R |= 0x03; /* set bits 0&1 of P3 control register 2 */
/* P40&P41 configure as AF out / OD / TTL */
break;
}
spp(I2C_PG);
I2CCTR &= I2C_CLEAR; /* i2c bus reset state */
I2COAR = 0; /* cell not active if only the 4 MSB of the address
match the cell address in case of slave mode use */
I2CFQR = attr;
I2CSTR2 &= ~I2C_ISCEN; /* disable the interrupt on stop condition */
I2CSTR2 |= I2C_SFEN; /* spike filter enabled */
I2CCTR &= ~I2C_CLEAR; /* enable i2c-bus interface */
fast_timers[I2CERRORTIMER] = 0; /* i2c-bus error counter */
bus_flags = 0x00;
}
/******************************************************************************
FUNCTION : I2C_IT interrupt
INPUTS : %
OUTPUTS :
DESCRIPTION : enable interrupt while interrupting with i2c_bus
but never use it for i2c-bus since disable the interrupt
on stop condition
*****************************************************************************/
#pragma interrupt (I2C_IT)
void I2C_IT(void)
{
SAVE_PPR;
EI;
spp (I2C_PG);
bus_flags |= I2C_INT_OK_F;
if ((I2CSTR1 & I2C_ACK_BIT) == I2C_ACK_BIT)
bus_flags &= ~I2C_ACK_F; /* No ACK : bus_flags.I2C_ACK_F = 0 */
else
bus_flags |= I2C_ACK_F; /* ACK : bus_flags.I2C_ACK_F = 1 */
RESTORE_PPR;
}
/******************************************************************************
FUNCTION : I2cReadByte
INPUTS : fast_timers[I2CERRORTIMER]
BOOL_ACK - sending ack-sign when receiving data
BOOL_STOP - creating stop-sign when receiving data
OUTPUTS : byte - read byte
bus_flags | BUS_GGOD
DESCRIPTION : read a byte.
*****************************************************************************/
unsigned char I2cReadByte (BOOL bool_ack,BOOL bool_stop)
{
unsigned char byte = 0;
SAVE_PPR;
if(bus_flags & I2C_GOOD_F)
{
spp(I2C_PG);
if(bool_ack)
I2CCTR &= ~I2C_SEND_ACK; /* read with ACK */
else
I2CCTR |= I2C_SEND_ACK; /* read without ACK */
fast_timers[I2CERRORTIMER] = I2C_TRANS_ERROR; /* bus trans. error waiting time */
I2CDR = 0xFF; /* acknowledge IT for I2C cell */
while (fast_timers[I2CERRORTIMER] && !( bus_flags & I2C_INT_OK_F ) )
bus_flags &= ~I2C_GOOD_F;
if (bus_flags & I2C_INT_OK_F) /* wait I2C interrupt */
{
bus_flags &= ~I2C_INT_OK_F; /* reset the flags */
bus_flags |= I2C_GOOD_F;
byte = I2CDR; /* read data from bus */
}
else
bool_stop = STOPTRUE; /* if fail stop the bus */
if(bool_stop)
I2CCTR |= I2C_STOP; /* stop sign */
}
RESTORE_PPR;
return byte;
}
/******************************************************************************
FUNCTION : I2cSendByte
INPUTS : byte - byte will be sned
bool_start -start with start-sign (TRUE) or not
bool_stop -terminate with stop-sign (TRUE) or not
OUTPUTS : bus_flags | BUS_GOOD
DESCRIPTION : Send a byte with ACK bit checking.
*****************************************************************************/
void I2cSendByte (unsigned char byte,BOOL bool_start,BOOL bool_stop)
{
SAVE_PPR;
if(bus_flags & I2C_GOOD_F)
{
spp(I2C_PG);
if(bool_start)
I2CCTR |= I2C_RSRT; /* ReStart generated before send */
I2CDR = byte; /* send data to bus */
fast_timers[I2CERRORTIMER] = I2C_TRANS_ERROR; /* bus trans. error waiting time */
while (fast_timers[I2CERRORTIMER] && !(bus_flags & I2C_INT_OK_F)); /* wait 9th clock pulse received */
bus_flags &= ~I2C_GOOD_F;
if (bus_flags & I2C_INT_OK_F)
{
bus_flags &= ~I2C_INT_OK_F;
if ( bus_flags & I2C_ACK_F ) /* if have ACK */
bus_flags |= I2C_GOOD_F;
else
bool_stop = STOPTRUE; /* if no ACK send stop sign */
}
if(bool_stop)
I2CCTR |= I2C_STOP;
}
RESTORE_PPR;
}
/******************************************************************************
FUNCTION : I2cCheck
INPUTS : fast_timers[I2CERRORTIMER]
OUTPUTS : TRUE -bus can be use
FALSE -bus can not be use
DESCRIPTION : check the bus to see whether it can use or not
*****************************************************************************/
BOOL I2cCheck(void)
{
SAVE_PPR;
spp(I2C_PG);
fast_timers[I2CERRORTIMER] = I2C_FREE_ERROR; /* initializes the I2cErrorTimer */
if( I2CSTR1 & I2C_ERROR )
{
I2CCTR |= I2C_RTI;
I2COAR = 0; /* cell not active if only the 4 MSB of the address
match the cell address in case of slave mode use */
I2CCTR &= I2C_CLEAR; /* i2c bus reset state */
I2CSTR2 &= ~I2C_ISCEN; /* disable the interrupt on stop condition */
I2CSTR2 |= I2C_SFEN; /* spike filter enabled */
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