bank.n

CPU的code banking技术实例： This Zip file contains five (3) folders: FastChip Project Files * This

// Netlist written January 19, 2001 4:34:57 PM PST
// By FastChip Version 2.1.1 Build 001212-1646
// Netlist last modified January 19, 2001 4:34:57 PM PST
netlist
module toplevel {
    net T0;
    net T1;
    net T2;
    net T2EX;
    net RXD_In;
    net RXD_Out;
    net TXD;
    net INTR0;
    net INTR1;
    net HPINT;
    net RSTCPU;
    net XTAL;
    net CPURST;
    net BusClock;
    net GBuf0;
    net GBuf1;
    net GBuf2;
    net GBuf3;
    net GBuf4;
    net GBuf5;
    net led [7:0];
    e5_sideband MCU (.rstc=RSTCPU, .cpurst=CPURST, :back_compatibility="false", :component_name="Sideband Signals");
    e5_clock_control Clocks (.busclk=BusClock, .gbuf0=GBuf0, .gbuf1=GBuf1, .gbuf2=GBuf2, .gbuf3=GBuf3, .gbuf4=GBuf4, .gbuf5=GBuf5, .xtal=XTAL, :component_name="Clock Control", :xtal_time="5", :clock_source="RING", :default_clock_value="0x00", :feedback_resistor="true", :issynconunblock5="true", :issynconunblock4="true", :issynconunblock3="true", :issynconunblock2="true", :issynconunblock1="true", :issynconunblock0="true", :iszerowhenblocked5="false", :iszerowhenblocked4="false", :iszerowhenblocked3="false", :busclk_freq="25.00", :iszerowhenblocked2="false", :iszerowhenblocked1="false", :iszerowhenblocked0="false", :isblockable5="true", :isblockable4="true", :isblockable3="true", :isblockable2="true", :isblockable1="true", :isblockable0="true", :isstoppedbusclkcsl="true");
    e5_MIU MIU (:address_size="512KB", :use_external_parallel_memory="true");
    _8032Timer0 Timer_0 (.t0=T0, :ist0pin="false", :tl0="0", :timer0gate="true", :t0_clock_source="0", :busminder="NONE", :t0_interrupt="false", :timer0enable="false", :th0="0", :isinputlowpower="true", :timer0mode="1", :component_name="Timer_0");
    _8032Timer1 Timer_1 (.t1=T1, :tl1="0", :ist1pin="false", :busminder="NONE", :timer1mode="1", :t1_interrupt="false", :timer1enable="false", :th1="0", :isinputlowpower="true", :timer1gate="true", :component_name="Timer_1", :t1_clock_source="0");
    _8032Timer2 Timer_2 (.t2=T2, .t2ex=T2EX, :ist2expin="false", :tl2="0", :t2_mode="0", :rcap2l="0", :rcap2h="0", :busminder="NONE", :t2_interrupt="false", :t2_clock_source="0", :ist2pin="false", :t2ex_enabled="false", :th2="0", :isinputlowpower="true", :component_name="8032 Timer 2", :t2_enabled="false");
    _8032UART UART (.rxdin=RXD_In, .rxdout=RXD_Out, .txd=TXD, :isrxdinpin="true", :serial_mode="-1", :th1="0", :drive="WEAK", :saden="0", :isrxdoutpin="true", :component_name="UART", :saddr="0", :autoaddress="false", :isinputlowpower="true", :doublerate="false", :txd_timer="0", :tb8="0", :rxd_timer="0", :busminder="NONE", :isoutputlowpower="true", :istxdpin="true", :rcap2l="0", :rcap2h="0", :ren="false", :uart_interrupt="false");
    _8032ICU Interrupt (.intr0=INTR0, .intr1=INTR1, .hpint=HPINT, :ea="false", :px1="false", :px0="false", :ex1="false", :ex0="false", :ps="false", :pwdi="false", :busminder="NONE", :isint0pin="false", :hysteresis="true", :ewdi="false", :pt2="false", :pt1="false", :isint1pin="false", :pt0="false", :component_name="Interrupt Control", :ehpi="false", :ishpintpin="false", :it1="false", :it0="false");
    e5_watchdog Watchdog (:wdt_interrupt="false", :component_name="Watchdog Timer", :interval="0", :wdt_reset="false");
    e5_dma0 DMA_0 (:crc_checking="false", :transfer_type="DMA_READ", :request_address="0", :intr_initialize="false", :block_request="false", :transfer_count="1", :continuous_init="false", :address_generation="INCREMENT", :intr_pending_ovfl="false", :intr_xfer_cnt="false", :component_name="DMA_0");
    e5_dma1 DMA_1 (:crc_checking="false", :transfer_type="DMA_READ", :request_address="0", :intr_initialize="false", :block_request="false", :transfer_count="1", :continuous_init="false", :address_generation="INCREMENT", :intr_pending_ovfl="false", :intr_xfer_cnt="false", :component_name="DMA_1");
    e5_power_mgmt Power (:pd_por_en="false", :pd_bclk_en="false", :pd_mode="NONE", :pd_osc_en="false", :pd_gbuf_en="false", :pd_cslbclk_en="false", :pd_io_en="false", :component_name="Power Management", :pd_powerdown_mode="false", :pd_idle_mode="false", :pd_xtal_en="false");
    e5_sfr SR ();
    e5_sram SRAM (:init_sram="true", :sram_init_value="0");
    '7seg' LED1 (.hex=led[3:0], .dp=null, :component_name="LED1", :drive="STRONG", :isoutputlowpower="true", :common_cathode="true");
    '7seg' LED2 (.hex=led[7:4], .dp=null, :component_name="LED2", :drive="STRONG", :isoutputlowpower="true", :common_cathode="true");
    cmdreg LED_Control (.q=led[7:0], :issfrspace="false", :iswriteonly="false", :relative="", :size="1", :address="", :component_width="8", :pitch="1", :ismatchdefined="false", :offset="0", :initv="0", :asyncv="0", :isaddressdefined="false", :symbolic="led", :space="DATA", :match1="", :match0="", :isplaced="false", :component_name="LED_Control", :isdataspace="true");
}