bank.tic

CPU的code banking技术实例： This Zip file contains five (3) folders: FastChip Project Files * This

// Timing constraints file written January 19, 2001 4:34:59 PM PST
// By FastChip Version 2.1.1 Build 001212-1646

// A tic (TIming Constraint file) holds timing constraints to be 
// implemented. Currently following two types of constraints are 
// supported.
// 
// set_max_delay <delayValue> -from <PS1>[,<PS2>,<PS3>,...] -to 
// <PS1>[,<PS2>,<PS3>,...] [-exclude <PS1>[,<PS2>,<PS3>,...]] [-through 
// <PS1>[,<PS2>,<PS3>,...]] 
// 
// create_clock -net <netName> -period <period> [-through <PS1>[,<PS2>,...]]
// [-exclude <PS1>[,<PS2>,...]] [-duty_cycle <highTime>]
// 
// <delayValue>, <period> and <highTime> should be positive numerical 
// value, the default unit is ns. <PS1>,<PS2>,<PS3> should be either pin 
// names from mapped netlist, pin wildcard names, or pin macros(
// ALL_INPUT_PINS, ALL_OUTPUT_PINS ALL_CLOCK_PINS(clkNet), 
// ALL_SETUP_PINS(clkNet), ALL_SOURCE_PINS(net), ALL_LOAD_PINS(net)), 
// <netName> should be name of the desired clock net from the 
// netlist file. All parameters in [] are optional, the rest are required.
// 
// The binder will issue and error message and stop if the required parameters 
// are either missing or contains invalid pin names. The binder will go on
// if the optional parameters contains invalid pin names
//  
// Here are some example timing constraints for a design with a 
// clock net "clk"
// 
// set_max_delay 10ns -from ALL_INPUT_PINS -to ALL_OUTPUT_PINS
// set_max_delay 3ns -from ALL_INPUT_PINS -to ALL_SETUP_PINS(clk)
// set_max_delay 3ns -from ALL_CLOCK_PINS(clk) -to ALL_OUTPUT_PINS
// set_max_delay 10ns -from ALL_SOURCE_PINS(net1) -to ALL_LOAD_PINS(net2)
// create_clock -net clk -period 30ns -duty_cycle 15ns