bank.h

CPU的code banking技术实例： This Zip file contains five (3) folders: FastChip Project Files * This

// EIP (Address 0xF8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     |     |     | PWDI|     |     |     |     |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  0  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


  
    WDCON &= 0xCF;    // Disable high-priority interrupt, clear HPI flag
    IE    &= 0x7A;    // Disable all interrupts, clear EX1 and EX0

    TCON  |= 0x00;    // Set IT1 and IT0 as defined
    TCON  &= 0x55;    // Clear interrupt flags in TCON register

    IP    &= 0xC0;    // Clear IP register
    IP    |= 0x00;    // Set priority values in IP register

    PWDI  =  0;       // Set priority bit for watchdog timer

    IE    |= 0x00;    // Enable EX1, EX0, and EA (enable all interrupts) as defined
    WDCON |= 0x00;    // Enable high-priority interrupt (HPI), as defined

}


// -------------------------------- Module Watchdog 


//**************************************************************
// The following are the function declarations for 'Watchdog'
//**************************************************************
//

//*********************************************
// Initialization Routine for 'Watchdog'
//*********************************************


void Watchdog_INIT () {

// WATCHDOG TIMER INITIALIZATION ROUTINE
// =====================================

//    Version = 0.8
//       Mode =
//       Type =


// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.


// WDCON (Address 0xd8) (IMPORTANT:  WDCON is timed-access protected!)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     | POR | EHPI| HPI | WDIF| WTRF| EWT | RWT |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  -  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// CKCON (Address 0x8e)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    | WD1 | WD0 | T2M | T1M | T0M |     |     |     |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  -  |  -  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// EIE (Address 0xe8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     |     |     | EWDI|     |     |     |     |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  0  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

    TA = 0xAA;      // Open timed-access window by writing 'AA' followed by
    TA = 0x55;      //     '55' to the TA register to access WDCON register
    RWT = 1;        // Reset watchdog timer to prevent MCU reset (WDCON.0)
    TA = 0xAA;      // Open timed-access window by writing 'AA' followed by
    TA = 0x55;      //     '55' to the TA register to access WDCON register
    WDCON &= 0xF0;  // Disable watchdog timer and clear watchdog flags
    CKCON |= 0x00;  // Set watchdog timer timeout value

    EWDI = 0;       // Enable or disabled watchdog interrupt (EWDI, EIE.4)

}


// -------------------------------- Module DMA_0 


//**************************************************************
// The following are the function declarations for 'DMA_0'
//**************************************************************

//*********************************************
// Initialization Routine for 'DMA_0'
//*********************************************

void DMA_0_INIT () {

// DMA CHANNEL 0 INITIALIZATION ROUTINE
// ====================================

//    Version = 1.0
//       Mode = DMA_READ


// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.



// DMACTRL0_0 (Address 0xff27)
//    +-----+-----+-----+------+-----+-----+-----+-----+
//    |  7  |  6  |  5  |   4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+======+=====+=====+=====+=====+
//    | W/R-| PAIR|BLOCK|SFTREQ| CONT| INIT|  EN | CLR |   BIT NAMES
//    +=====+=====+=====+======+=====+=====+=====+=====+
//    |  0  |  0  |  0  |   0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+------+-----+-----+-----+-----+


// DMACTRL0_1 (Address 0xff28)
//    +-----+-----+-----+-----+-----+------+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |   2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+======+=====+=====+
//    |     |     |     |     |     |CRC_EN|ADRM1|ADRM0|   BIT NAMES
//    +=====+=====+=====+=====+=====+======+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |   0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+------+-----+-----+


// DMAEINT0 (Address 0xff29)
//    +-----+-----+-----+-----+-----+------+-------+-----+
//    |  7  |  6  |  5  |  4  |  3  |   2  |   1   |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+======+=======+=====+
//    |     |     |     |     |     |OVR_EN|INIT_EN|TC_EN|   BIT NAMES
//    +=====+=====+=====+=====+=====+======+=======+=====+
//    |  0  |  0  |  0  |  0  |  0  |   0  |   0   |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+------+-------+-----+


// Set up the DMA Channel 0 control register
// -----------------------------------------
    DMACTRL0_0 = 0x01;                // Clear DMA channel 0 control register
    DMACTRL0_1 = 0x00;                // Set high-byte settings in control register
    DMACTRL0_0 = 0x00;                // Set low-byte settings in control register


// Set up the transfer count
// -------------------------
// NOTE:  TRANSFER_COUNT = (BYTE_COUNT - 1)
    DMASCNT0_0 = 0x00;                // Move transfer count low-byte of DMA 0 transfer count register
    DMASCNT0_1 = 0x00;                // Move transfer count mid-byte of DMA 0 transfer count register
    DMASCNT0_2 = 0x00;                // Move transfer count high-byte of DMA 0 transfer count register

    
// Enable the DMA Channel 0 interrupts
// -----------------------------------
    DMAINT0    = 0x07;                // Clear DMA channel 0 interrupt flags by writing ones to bit
    DMAEINT0   = 0x00;                // Enable DMA channel 0 interrupts


// NOTE:  Must still set up the Starting Address registers and
// ====   enable and initialize the channel before starting any transfers.
//
// DMA Start Address is a 32-bit _physical_ address value stored in the following locations
//
// DMASADR0_0 = Start_Address[7:0]
// DMASADR0_1 = Start_Address[15:8]
// DMASADR0_2 = Start_Address[23:16]
// DMASADR0_3 = Start_Address[31:24]

}


// -------------------------------- Module DMA_1 


//**************************************************************
// The following are the function declarations for 'DMA_1'
//**************************************************************

//*********************************************
// Initialization Routine for 'DMA_1'
//*********************************************

void DMA_1_INIT () {

// DMA CHANNEL 1 INITIALIZATION ROUTINE
// ====================================

//    Version = 1.0
//       Mode = DMA_READ


// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.



// DMACTRL1_0 (Address 0xff3b)
//    +-----+-----+-----+------+-----+-----+-----+-----+
//    |  7  |  6  |  5  |   4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+======+=====+=====+=====+=====+
//    | W/R-| PAIR|BLOCK|SFTREQ| CONT| INIT|  EN | CLR |   BIT NAMES
//    +=====+=====+=====+======+=====+=====+=====+=====+
//    |  0  |  0  |  0  |   0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+------+-----+-----+-----+-----+


// DMACTRL1_1 (Address 0xff3c)
//    +-----+-----+-----+-----+-----+------+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |   2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+======+=====+=====+
//    |     |     |     |     |     |CRC_EN|ADRM1|ADRM0|   BIT NAMES
//    +=====+=====+=====+=====+=====+======+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |   0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+------+-----+-----+


// DMAEINT1 (Address 0xff3d)
//    +-----+-----+-----+-----+-----+------+-------+-----+
//    |  7  |  6  |  5  |  4  |  3  |   2  |   1   |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+======+=======+=====+
//    |     |     |     |     |     |OVR_EN|INIT_EN|TC_EN|   BIT NAMES
//    +=====+=====+=====+=====+=====+======+=======+=====+
//    |  0  |  0  |  0  |  0  |  0  |   0  |   0   |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+------+-------+-----+

    
// Set up the DMA Channel 1 control register
// -----------------------------------------
    DMACTRL1_0 = 0x01;                // Clear DMA channel 1 control register
    DMACTRL1_1 = 0x00;                // Set high-byte settings in control register
    DMACTRL1_0 = 0x00;                // Set low-byte settings in control register


// Set up the transfer count
// -------------------------
// NOTE:  TRANSFER_COUNT = (BYTE_COUNT - 1)
    DMASCNT1_0 = 0x00;                // Move transfer count low-byte of DMA 1 transfer count register
    DMASCNT1_1 = 0x00;                // Move transfer count mid-byte of DMA 1 transfer count register
    DMASCNT1_2 = 0x00;                // Move transfer count high-byte of DMA 1 transfer count register


// Enable the DMA Channel 1 interrupts
// -----------------------------------
    DMAINT1    = 0x07;                // Clear DMA channel 1 interrupt flags by writing ones to bit
    DMAEINT1   = 0x00;                // Enable DMA channel 1 interrupts


// NOTE:  Must still set up the Starting Address registers and
// ====   enable and initialize the channel before starting any transfers.
//
// DMA Start Address is a 32-bit _physical_ address value stored in the following locations
//
// DMASADR1_0 = Start_Address[7:0]
// DMASADR1_1 = Start_Address[15:8]
// DMASADR1_2 = Start_Address[23:16]
// DMASADR1_3 = Start_Address[31:24]

}


// -------------------------------- Module Power 

//**************************************************************
// The following are the function declarations for 'Power'
//**************************************************************

//*********************************************
// Initialization Routine for 'Power'
//*********************************************


void Power_INIT () {

// POWER MANAGEMENT INITIALIZATION ROUTINE
// =======================================
//    Version = 0.8
//       Mode =
//       Type =


// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.

// PCON (Address 0x87)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    | SMOD|SMOD0|     |     | GF1 | GF0 |  PD | IDL |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  -  |  -  |  -  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// PWDSEL (Address XDATA 0xff62)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     |     | PIO | XTAL| OSC | GBUF| CSL | BCLK|   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// PORCTRL (Address XDATA 0xff63)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     |     |     |     |     |     |     |PORCT|   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  -  |  -  |  -  |  -  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


    PWDSEL  = 0x00;        // Set power-down options in PWDSEL

    PORCTRL = 0x00;        // Write the POR enable/disable value into the PORCTRL

    PCON   &= 0xfc;        // Clear power-down bit (PD, PCON.1) and idle bit (IDL, PCON.0)
}


// ========= PROJECT INITIALIZATION FUNCTION ======

// You can use the -DNO_PROJ_INIT compiler flag
// to exclude the following code

#ifndef NO_PROJ_INIT

void bank_INIT () {
    Timer_0_INIT();
    Timer_1_INIT();
    Timer_2_INIT();
    UART_INIT();
    Interrupt_INIT();
    Watchdog_INIT();
    DMA_0_INIT();
    DMA_1_INIT();
    Power_INIT();
}


#endif /* NO_PROJ_INIT */

#endif /* PROTOTYPE_ONLY */