bank.h

CPU的code banking技术实例： This Zip file contains five (3) folders: FastChip Project Files * This

    TMOD |= 0x09;	// Set appropriate bits for Timer 0
    TL0 = 0x00;		// Set Timer 0 low byte to user-defined value
    TH0 = 0x00;		// Set Timer 0 high byte to user-defined value

    CKCON &= 0x0F7; 	// Timer 0 clock source is (BusClock / 12) (CKCON.3)

    ET0 = 0;            // Set or clear Timer 0 interrupt (IE.1)

}


// -------------------------------- Module Timer_1 


//**************************************************************
// The following are the function declarations for 'Timer_1'
//**************************************************************
//

//*********************************************
// Initialization Routine for 'Timer_1'
//*********************************************


void Timer_1_INIT () {

// TIMER 1 INITIALIZATION ROUTINE
// ==============================

//    Version = 0.8
//       Mode = 1
//       Type = Timer


// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.


// TMOD (Address 0x89)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |        Timer 1        |        Timer 0        |
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    | GATE| C/T |  M1 |  M0 | GATE| C/T |  M1 |  M0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  1  |  0  |  0  |  1  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// TCON (Address 0x88)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    | TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  0  |  -  |  -  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// CKCON (Address 0x8e)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    | WD1 | WD0 | T2M | T1M | T0M |     |     |     |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  0  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

// IE (Address 0xA8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  EA |     | ET2 |  ES | ET1 | EX1 | ET0 | EX0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  -  |  0  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

    TR1 = 0;		// Disable Timer 1 (TCON.6)
    TMOD &= 0x0F;	// Clear Timer 1 bits (upper nibble) in TMOD register
    TMOD |= 0x90;	// Set appropriate bits for Timer 1
    TL1 = 0x00;		// Set Timer 1 low byte to user-defined value
    TH1 = 0x00;		// Set Timer 1 high byte to user-defined value

    CKCON &= 0x0EF;	// Timer 1 clock source is (BusClock / 12) (CKCON.4)

    ET1 = 0;            // Set or clear Timer 1 interrupt (IE.3)

}


// -------------------------------- Module Timer_2 

//**************************************************************
// The following are the function declarations for 'Timer_2'
//**************************************************************

//*********************************************
// Initialization Routine for 'Timer_2'
//*********************************************


void Timer_2_INIT () {

// TIMER 2 INITIALIZATION ROUTINE
// ==============================

//         Version = 0.8
//            Mode = 0

// RCAP2H (Address 0xCB) = 000H
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

// RCAP2L (Address 0xCA) = 000H
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// TH2 (Address 0xCD) = 000H
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// TL2 (Address 0xCC) = 000H
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// CKCON (Address 0x8E)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    | WD1 | WD0 | T2M | T1M | T0M |     |     |     |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  0  |  -  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// T2MOD (Address 0xC9)
//    +-----+-----+-----+-----+-----+-----+-----+-------+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |   0   |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-------+
//    |     |     |     |     |     |     |     |  DCEN |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=======+
//    |  -  |  -  |  -  |  -  |  -  |  -  |  -  |   0   |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-------+


// T2CON (Address 0xC8)
//    +-----+-----+-----+-----+-----+-----+-----+-------+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |   0   |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-------+
//    | TF2 | EXF2| RCLK| TCLK|EXEN2| TR2 | C/T2| CP/RL2|   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=======+
//    |  -  |  -  |  -  |  -  |  0  |  0  |  0  |   0   |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-------+


// IE (Address 0xA8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  EA |     | ET2 |  ES | ET1 | EX1 | ET0 | EX0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  0  |  -  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

    TR2 = 0;		//Halt Timer 2, allows safe writing of RCAP2x registers (T2CON.2)
    RCAP2H = 0x00;	//Define high-byte in Timer 2 reload register
    RCAP2L = 0x00;	//Define low-byte in Timer 2 reload register
    TH2 = 0x00;		//Define high-byte in Timer 2 counter register
    TL2 = 0x00;		//Define low-byte in Timer 2 counter register
    T2MOD = 0x00;	//Define down-count enable bit

    CKCON &= 0xdf;	//Timer 2 clock source is (BusClock / 12) (CKCON.5)

    ET2 = 0;            // Set or clear Timer 2 interrupt (IE.5)

    T2CON &= 0xff;	//Clear appropriate bits in T2CON
    T2CON |= 0x00;	//Set appropriate bits in T2CON

}


// -------------------------------- Module UART 


//**************************************************************
// The following are the function declarations for 'UART'
//**************************************************************
//

//*********************************************
// Initialization Routine for 'UART'
//*********************************************


void UART_INIT () {

// SERIAL PORT INITIALIZATION ROUTINE
// ==================================

//         Version = 0.9
//            Mode = -1
//        Receiver = Disabled
// Auto Addressing = Disabled


// ----- Set up control registers for UART
// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.


// SCON (Address 0x98)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    | SM0 | SM1 | SM2 | REN | TB8 | RB8 |  TI |  RI |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// SBUF (Address 0x99) = 000H
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  0  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// PCON (Address 0x87)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    | SMOD|     |     |     | GF1 | GF0 | PDE | IDLE|   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  -  |  -  |  -  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+

// IE (Address 0xA8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  EA |     | ET2 |  ES | ET1 | EX1 | ET0 | EX0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  -  |  0  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


    SCON = 0x00;	// Set up serial port control register
    PCON |= 0x00;	// Set double-rate bit, SMOD, if enabled

}


// -------------------------------- Module Interrupt 

//**************************************************************
// The following are the function declarations for 'Interrupt'
//**************************************************************

//*********************************************
// Initialization Routine for 'Interrupt'
//*********************************************

void Interrupt_INIT () {

// INTERRUPT CONTROLLER INITIALIZATION ROUTINE
// ===========================================

//         Version = 0.8

// This initialization routing modifies the following registers:
// Note:  A dash (-) in a register location indicates an untouched bit.

// NOTES:
// =====
// Interrupt vector locations for the Triscend E5
//
// ---------------------------------+------------+---------------
//         INTERRUPT                |   VECTOR   |  KEIL INTR #
// ---------------------------------+------------+---------------
//  High-Priority Interrupt (HPINT)     0033h           6
//  External Interrupt (INT0)           0003h           0
//  Timer 0                             000Bh           1
//  External Interrupt (INT1)           0013h           2
//  Timer 1                             001Bh           3
//  UART                                0023h           4
//  Timer 2                             002Bh           5
//  DMA Controller                      003Bh           7
//  -- Reserved (hardware breakpoint)   0043h           8
//  -- Reserved (JTAG controller)       004Bh           9
//  -- Reserved (software breakpoint)   0053h          10
//  Watchdog Timer                      0063h          12


// Example Keil code for interrupt service routines (Watchdog timer)
//
// static void watchdogISR() interrupt 12 {
//     <your application code here>
// }


//  WDCON (Address 0xd8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |     | POR | EHPI| HPI | WDIF| WTRF| EWT | RWT |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  0  |  0  |  -  |  -  |  -  |  -  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// TCON (Address 0x88)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    | TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  -  |  0  |  -  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+


// IE (Address 0xA8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  EA |     | ET2 |  ES | ET1 | EX1 | ET0 | EX0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  0  |  -  |  -  |  -  |  -  |  0  |  -  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//
//    NOTE:
//    ----
//       ET2 controlled by Timer 2 module
//       ES controlled by UART module
//       ET1 controlled by Timer 1 module
//       ET0 controlled by Timter 0 module


// IP (Address 0xB8)
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |   BIT LOCATIONS
//    +-----+-----+-----+-----+-----+-----+-----+-----+
//    |     |     | PT2 |  PS | PT1 | PX1 | PT0 | PX0 |   BIT NAMES
//    +=====+=====+=====+=====+=====+=====+=====+=====+
//    |  -  |  -  |  0  |  0  |  0  |  0  |  0  |  0  |   REGISTER VALUE
//    +-----+-----+-----+-----+-----+-----+-----+-----+