📄 bank.h
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// Generated 1/24/01 8:09 PM By FastChip Version 2.1.1 Build 001212-1646
//////////////////////////////////////////////////////////////////////////////
//
// ----------------------------------
// ------ GENERATED CODE --------
// ----------------------------------
// The code in this header file was generated automatically for your
// project by Triscend FastChip. Please DO NOT EDIT this header file.
// It will be overwritten the next time FastChip generates code for
// your project.
//
//////////////////////////////////////////////////////////////////////////////
//======== Required symbol and macro definitions ========
#ifdef TASKING_TOOLS
# define SFR_BIT(name,location) _sfrbit name _at( location );
# define SFR_BYTE(name,location) _sfrbyte name _at( location );
#else /* TASKING_TOOLS */
# define SFR_BIT(name,location) sbit name = location;
# define SFR_BYTE(name,location) sfr name = location;
#endif /* TASKING_TOOLS */
// You must use the -DPROTOYPE_ONLY compiler flag
// for all files other than the main source file
#ifdef PROTOTYPE_ONLY
# ifdef TASKING_TOOLS
# define CHAR_XDATA(name,location) extern volatile unsigned char _xdat name;
# define CHAR_ARRAY_XDATA(name,location,size) extern volatile unsigned char _xdat name[size];
# else /* TASKING_TOOLS */
# define CHAR_XDATA(name,location) extern volatile unsigned char xdata name;
# define CHAR_ARRAY_XDATA(name,location,size) extern volatile unsigned char xdata name[size];
# endif /* TASKING_TOOLS */
#else /* PROTOTYPE_ONLY */
# ifdef TASKING_TOOLS
# define CHAR_XDATA(name,location) volatile unsigned char _xdat name _at( location );
# define CHAR_ARRAY_XDATA(name,location,size) volatile unsigned char _xdat name[size] _at( location );
# else /* TASKING_TOOLS */
# define CHAR_XDATA(name,location) volatile unsigned char xdata name _at_ location;
# define CHAR_ARRAY_XDATA(name,location,size) volatile unsigned char xdata name[size] _at_ location;
# endif /* TASKING_TOOLS */
#endif /* PROTOTYPE_ONLY */
// ========= BEGIN SOFT MODULE REGISTER DECLARATIONS ======
CHAR_XDATA (led,0xefff)
// ========== END SOFT MODULE REGISTER DECLARATIONS =======
//======== E5 byte addressable SFR registers ========
// -- reserved (P0) --
SFR_BYTE( SP , 0x81)
SFR_BYTE( DPL , 0x82)
SFR_BYTE( DPH , 0x83)
SFR_BYTE( DPL1 , 0x84)
SFR_BYTE( DPH1 , 0x85)
SFR_BYTE( DPS , 0x86)
SFR_BYTE( PCON , 0x87)
SFR_BYTE( TCON , 0x88)
SFR_BYTE( TMOD , 0x89)
SFR_BYTE( TL0 , 0x8a)
SFR_BYTE( TL1 , 0x8b)
SFR_BYTE( TH0 , 0x8c)
SFR_BYTE( TH1 , 0x8d)
SFR_BYTE( CKCON , 0x8e)
// -- reserved (P1) --
SFR_BYTE( SCON , 0x98)
SFR_BYTE( SBUF , 0x99)
// -- reserved (P2) --
SFR_BYTE( IE , 0xa8)
SFR_BYTE( SADDR , 0xa9)
// -- reserved (P3) --
SFR_BYTE( IP , 0xb8)
SFR_BYTE( SADEN , 0xb9)
SFR_BYTE( TA , 0xc7)
SFR_BYTE( T2CON , 0xc8)
SFR_BYTE( T2MOD , 0xc9)
SFR_BYTE( RCAP2L , 0xca)
SFR_BYTE( RCAP2H , 0xcb)
SFR_BYTE( TL2 , 0xcc)
SFR_BYTE( TH2 , 0xcd)
SFR_BYTE( PSW , 0xd0)
SFR_BYTE( WDCON , 0xd8)
SFR_BYTE( ACC , 0xe0)
SFR_BYTE( EIE , 0xe8)
SFR_BYTE( B , 0xf0)
SFR_BYTE( EIP , 0xf8)
//======== E5 bit addressable SFR registers ========
//---------------------------- TCON
SFR_BIT( TF1 , 0x8f)
SFR_BIT( TR1 , 0x8e)
SFR_BIT( TF0 , 0x8d)
SFR_BIT( TR0 , 0x8c)
SFR_BIT( IE1 , 0x8b)
SFR_BIT( IT1 , 0x8a)
SFR_BIT( IE0 , 0x89)
SFR_BIT( IT0 , 0x88)
//---------------------------- SCON
SFR_BIT( SM0 , 0x9f)
SFR_BIT( SM1 , 0x9e)
SFR_BIT( SM2 , 0x9d)
SFR_BIT( REN , 0x9c)
SFR_BIT( TB8 , 0x9b)
SFR_BIT( RB8 , 0x9a)
SFR_BIT( TI , 0x99)
SFR_BIT( RI , 0x98)
//---------------------------- IE
SFR_BIT( EA , 0xaf)
// -- reserved --
SFR_BIT( ET2 , 0xad)
SFR_BIT( ES , 0xac)
SFR_BIT( ET1 , 0xab)
SFR_BIT( EX1 , 0xaa)
SFR_BIT( ET0 , 0xa9)
SFR_BIT( EX0 , 0xa8)
//---------------------------- IP
// -- reserved --
// -- reserved --
SFR_BIT( PT2 , 0xbd)
SFR_BIT( PS , 0xbc)
SFR_BIT( PT1 , 0xbb)
SFR_BIT( PX1 , 0xba)
SFR_BIT( PT0 , 0xb9)
SFR_BIT( PX0 , 0xb8)
//---------------------------- T2CON
SFR_BIT( TF2 , 0xcf)
SFR_BIT( EXF2 , 0xce)
SFR_BIT( RCLK , 0xcd)
SFR_BIT( TCLK , 0xcc)
SFR_BIT( EXEN2 , 0xcb)
SFR_BIT( TR2 , 0xca)
SFR_BIT( C_T2 , 0xc9)
SFR_BIT( CP_RL2 , 0xc8)
//---------------------------- PSW
SFR_BIT( CY , 0xd7)
SFR_BIT( AC , 0xd6)
SFR_BIT( F0 , 0xd5)
SFR_BIT( RS1 , 0xd4)
SFR_BIT( RS0 , 0xd3)
SFR_BIT( OV , 0xd2)
// -- reserved --
SFR_BIT( P , 0xd0)
//---------------------------- WDCON
// -- reserved --
SFR_BIT( POR , 0xde)
SFR_BIT( EHPI , 0xdd)
SFR_BIT( HPI , 0xdc)
SFR_BIT( WDIF , 0xdb)
SFR_BIT( WTRF , 0xda)
SFR_BIT( EWT , 0xd9)
SFR_BIT( RWT , 0xd8)
//---------------------------- EIE
// -- reserved --
// -- reserved --
// -- reserved --
SFR_BIT( EWDI , 0xec)
// -- reserved --
// -- reserved --
// -- reserved --
// -- reserved --
//---------------------------- EIP
// -- reserved --
// -- reserved --
// -- reserved --
SFR_BIT( PWDI , 0xfc)
// -- reserved --
// -- reserved --
// -- reserved --
// -- reserved --
//========= Visible CRU Registers ========
#define E5CRU_VISIBLE_BASE_ADDR 0xf000
CHAR_XDATA ( CMAP0_TAR, 0xff00 )
CHAR_XDATA ( CMAP0_ALT, 0xff01 )
CHAR_XDATA ( CMAP1_TAR_0, 0xff02 )
CHAR_XDATA ( CMAP1_TAR_1, 0xff03 )
CHAR_XDATA ( CMAP1_TAR_2, 0xff04 )
CHAR_XDATA ( CMAP1_SRC, 0xff05 )
CHAR_XDATA ( CMAP1_CTL, 0xff06 )
CHAR_XDATA ( CMAP1_ALT, 0xff07 )
CHAR_XDATA ( CMAP2_TAR_0, 0xff08 )
CHAR_XDATA ( CMAP2_TAR_1, 0xff09 )
CHAR_XDATA ( CMAP2_TAR_2, 0xff0a )
CHAR_XDATA ( CMAP2_SRC, 0xff0b )
CHAR_XDATA ( CMAP2_CTL, 0xff0c )
CHAR_XDATA ( CMAP2_ALT, 0xff0d )
CHAR_XDATA ( DMAP0_TAR, 0xff0e )
CHAR_XDATA ( DMAP1_TAR_0, 0xff0f )
CHAR_XDATA ( DMAP1_TAR_1, 0xff10 )
CHAR_XDATA ( DMAP1_TAR_2, 0xff11 )
CHAR_XDATA ( DMAP1_SRC, 0xff12 )
CHAR_XDATA ( DMAP1_CTL, 0xff13 )
CHAR_XDATA ( DMAP2_TAR_0, 0xff14 )
CHAR_XDATA ( DMAP2_TAR_1, 0xff15 )
CHAR_XDATA ( DMAP2_TAR_2, 0xff16 )
CHAR_XDATA ( DMAP2_SRC, 0xff17 )
CHAR_XDATA ( DMAP2_CTL, 0xff18 )
CHAR_XDATA ( DMAP3_TAR, 0xff19 )
CHAR_XDATA ( DMAP3_SRC, 0xff1a )
CHAR_XDATA ( DMAP3_CTL, 0xff1b )
// -- reserved --
// -- reserved --
// -- reserved --
// -- reserved --
CHAR_XDATA ( DMASADR0_0, 0xff20 )
CHAR_XDATA ( DMASADR0_1, 0xff21 )
CHAR_XDATA ( DMASADR0_2, 0xff22 )
CHAR_XDATA ( DMASADR0_3, 0xff23 )
CHAR_XDATA ( DMASCNT0_0, 0xff24 )
CHAR_XDATA ( DMASCNT0_1, 0xff25 )
CHAR_XDATA ( DMASCNT0_2, 0xff26 )
CHAR_XDATA ( DMACTRL0_0, 0xff27 )
CHAR_XDATA ( DMACTRL0_1, 0xff28 )
CHAR_XDATA ( DMAEINT0, 0xff29 )
CHAR_XDATA ( DMAINT0, 0xff2a )
CHAR_XDATA ( DMACADR0_0, 0xff2b )
CHAR_XDATA ( DMACADR0_1, 0xff2c )
CHAR_XDATA ( DMACADR0_2, 0xff2d )
CHAR_XDATA ( DMACADR0_3, 0xff2e )
CHAR_XDATA ( DMACCNT0_0, 0xff2f )
CHAR_XDATA ( DMACCNT0_1, 0xff30 )
CHAR_XDATA ( DMACCNT0_2, 0xff31 )
CHAR_XDATA ( DMAPREQ0_0, 0xff32 )
CHAR_XDATA ( DMAPREQ0_1, 0xff33 )
CHAR_XDATA ( DMASADR1_0, 0xff34 )
CHAR_XDATA ( DMASADR1_1, 0xff35 )
CHAR_XDATA ( DMASADR1_2, 0xff36 )
CHAR_XDATA ( DMASADR1_3, 0xff37 )
CHAR_XDATA ( DMASCNT1_0, 0xff38 )
CHAR_XDATA ( DMASCNT1_1, 0xff39 )
CHAR_XDATA ( DMASCNT1_2, 0xff3a )
CHAR_XDATA ( DMACTRL1_0, 0xff3b )
CHAR_XDATA ( DMACTRL1_1, 0xff3c )
CHAR_XDATA ( DMAEINT1, 0xff3d )
CHAR_XDATA ( DMAINT1, 0xff3e )
CHAR_XDATA ( DMACADR1_0, 0xff3f )
CHAR_XDATA ( DMACADR1_1, 0xff40 )
CHAR_XDATA ( DMACADR1_2, 0xff41 )
CHAR_XDATA ( DMACADR1_3, 0xff42 )
CHAR_XDATA ( DMACCNT1_0, 0xff43 )
CHAR_XDATA ( DMACCNT1_1, 0xff44 )
CHAR_XDATA ( DMACCNT1_2, 0xff45 )
CHAR_XDATA ( DMAPREQ1_0, 0xff46 )
CHAR_XDATA ( DMAPREQ1_1, 0xff47 )
CHAR_XDATA ( DMACRC_0, 0xff48 )
CHAR_XDATA ( DMACRC_1, 0xff49 )
CHAR_XDATA ( PROTECT, 0xff60 )
CHAR_XDATA ( SECURITY, 0xff61 )
CHAR_XDATA ( PWDSEL, 0xff62 )
CHAR_XDATA ( PORCTRL, 0xff63 )
CHAR_XDATA ( DMAP4_TAR_0, 0xff80 )
CHAR_XDATA ( DMAP4_TAR_1, 0xff81 )
CHAR_XDATA ( DMAP4_TAR_2, 0xff82 )
CHAR_XDATA ( DMAP4_SRC, 0xff83 )
CHAR_XDATA ( DMAP4_CTL, 0xff84 )
CHAR_XDATA ( DMAP5_TAR_0, 0xff85 )
CHAR_XDATA ( DMAP5_TAR_1, 0xff86 )
CHAR_XDATA ( DMAP5_TAR_2, 0xff87 )
CHAR_XDATA ( DMAP5_SRC, 0xff88 )
CHAR_XDATA ( DMAP5_CTL, 0xff89 )
//========= End Visible CRU Registers ========
#ifdef PROTOTYPE_ONLY
// ========= PROJECT INITIALIZATION FUNCTION ======
// You can use the -DNO_PROJ_INIT compiler flag
// to exclude the following code
#ifndef NO_PROJ_INIT
extern void bank_INIT ();
#endif /* NO_PROJ_INIT */
// ========= MODULE INITIALIZATION FUNCTION ======
extern void Timer_0_INIT();
extern void Timer_1_INIT();
extern void Timer_2_INIT();
extern void UART_INIT();
extern void Interrupt_INIT();
extern void Watchdog_INIT();
extern void DMA_0_INIT();
extern void DMA_1_INIT();
extern void Power_INIT();
#else /* PROTOTYPE_ONLY */
// -------------------------------- Module Timer_0
//**************************************************************
// The following are the function declarations for 'Timer_0'
//**************************************************************
//*********************************************
// Initialization Routine for 'Timer_0'
//*********************************************
void Timer_0_INIT () {
// TIMER 0 INITIALIZATION ROUTINE
// ==============================
// Version = 0.8
// Mode = 1
// Type = Timer
// This initialization routing modifies the following registers:
// Note: A dash (-) in a register location indicates an untouched bit.
// TMOD (Address 0x89)
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | Timer 1 | Timer 0 |
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | BIT LOCATIONS
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | GATE| C/T | M1 | M0 | GATE| C/T | M1 | M0 | BIT NAMES
// +=====+=====+=====+=====+=====+=====+=====+=====+
// | - | - | - | - | 1 | 0 | 0 | 1 | REGISTER VALUE
// +-----+-----+-----+-----+-----+-----+-----+-----+
// TCON (Address 0x88)
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | BIT LOCATIONS
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 | BIT NAMES
// +=====+=====+=====+=====+=====+=====+=====+=====+
// | - | - | - | 0 | - | - | - | - | REGISTER VALUE
// +-----+-----+-----+-----+-----+-----+-----+-----+
// CKCON (Address 0x8e)
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | BIT LOCATIONS
// +=====+=====+=====+=====+=====+=====+=====+=====+
// | WD1 | WD0 | T2M | T1M | T0M | | | | BIT NAMES
// +=====+=====+=====+=====+=====+=====+=====+=====+
// | - | - | - | - | 0 | - | - | - | REGISTER VALUE
// +-----+-----+-----+-----+-----+-----+-----+-----+
// IE (Address 0xA8)
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | BIT LOCATIONS
// +-----+-----+-----+-----+-----+-----+-----+-----+
// | EA | | ET2 | ES | ET1 | EX1 | ET0 | EX0 | BIT NAMES
// +=====+=====+=====+=====+=====+=====+=====+=====+
// | - | - | - | - | - | - | 0 | - | REGISTER VALUE
// +-----+-----+-----+-----+-----+-----+-----+-----+
TR0 = 0; // Disable Timer 0 (TCON.4)
TMOD &= 0x0F0; // Clear Timer 0 bits (lower nibble) in TMOD register
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