📄 stm32l1xx.h
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#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_SQR3 register *******************/
#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_SQR4 register *******************/
#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_SQR5 register *******************/
#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit⌨️ 快捷键说明
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