📄 stm32l1xx.h
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#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define RI ((RI_TypeDef *) RI_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
/******************* Bit definition for ADC_CR1 register ********************/
#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
/****************** Bit definition for ADC_SMPR1 register *******************/
#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
/****************** Bit definition for ADC_SMPR3 register *******************/
#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
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