📄 stm32f10x_usart.txt
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;;;203 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;204 /* Set STOP[13:12] bits according to USART_StopBits value */
;;;205 tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
000024 88f0 LDRH r0,[r6,#6]
000026 4304 ORRS r4,r4,r0
;;;206
;;;207 /* Write to USART CR2 */
;;;208 USARTx->CR2 = (uint16_t)tmpreg;
000028 822c STRH r4,[r5,#0x10]
;;;209
;;;210 /*---------------------------- USART CR1 Configuration -----------------------*/
;;;211 tmpreg = USARTx->CR1;
00002a 89ac LDRH r4,[r5,#0xc]
;;;212 /* Clear M, PCE, PS, TE and RE bits */
;;;213 tmpreg &= CR1_CLEAR_Mask;
00002c f64e10f3 MOV r0,#0xe9f3
000030 4004 ANDS r4,r4,r0
;;;214 /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;215 /* Set the M bits according to USART_WordLength value */
;;;216 /* Set PCE and PS bits according to USART_Parity value */
;;;217 /* Set TE and RE bits according to USART_Mode value */
;;;218 tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
000032 88b0 LDRH r0,[r6,#4]
000034 8931 LDRH r1,[r6,#8]
000036 4308 ORRS r0,r0,r1
000038 8971 LDRH r1,[r6,#0xa]
00003a 4308 ORRS r0,r0,r1
00003c 4304 ORRS r4,r4,r0
;;;219 USART_InitStruct->USART_Mode;
;;;220 /* Write to USART CR1 */
;;;221 USARTx->CR1 = (uint16_t)tmpreg;
00003e 81ac STRH r4,[r5,#0xc]
;;;222
;;;223 /*---------------------------- USART CR3 Configuration -----------------------*/
;;;224 tmpreg = USARTx->CR3;
000040 8aac LDRH r4,[r5,#0x14]
;;;225 /* Clear CTSE and RTSE bits */
;;;226 tmpreg &= CR3_CLEAR_Mask;
000042 f64f40ff MOV r0,#0xfcff
000046 4004 ANDS r4,r4,r0
;;;227 /* Configure the USART HFC -------------------------------------------------*/
;;;228 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;229 tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
000048 89b0 LDRH r0,[r6,#0xc]
00004a 4304 ORRS r4,r4,r0
;;;230 /* Write to USART CR3 */
;;;231 USARTx->CR3 = (uint16_t)tmpreg;
00004c 82ac STRH r4,[r5,#0x14]
;;;232
;;;233 /*---------------------------- USART BRR Configuration -----------------------*/
;;;234 /* Configure the USART Baud Rate -------------------------------------------*/
;;;235 RCC_GetClocksFreq(&RCC_ClocksStatus);
00004e a801 ADD r0,sp,#4
000050 f7fffffe BL RCC_GetClocksFreq
;;;236 if (usartxbase == USART1_BASE)
000054 481f LDR r0,|L12.212|
000056 4287 CMP r7,r0
000058 d102 BNE |L12.96|
;;;237 {
;;;238 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
00005a f8dda010 LDR r10,[sp,#0x10]
00005e e001 B |L12.100|
|L12.96|
;;;239 }
;;;240 else
;;;241 {
;;;242 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
000060 f8dda00c LDR r10,[sp,#0xc]
|L12.100|
;;;243 }
;;;244
;;;245 /* Determine the integer part */
;;;246 if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
000064 89a8 LDRH r0,[r5,#0xc]
000066 f4104f00 TST r0,#0x8000
00006a d008 BEQ |L12.126|
;;;247 {
;;;248 /* Integer part computing in case Oversampling mode is 8 Samples */
;;;249 integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
00006c eb0a00ca ADD r0,r10,r10,LSL #3
000070 eb00100a ADD r0,r0,r10,LSL #4
000074 6831 LDR r1,[r6,#0]
000076 0049 LSLS r1,r1,#1
000078 fbb0f8f1 UDIV r8,r0,r1
00007c e007 B |L12.142|
|L12.126|
;;;250 }
;;;251 else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
;;;252 {
;;;253 /* Integer part computing in case Oversampling mode is 16 Samples */
;;;254 integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
00007e eb0a00ca ADD r0,r10,r10,LSL #3
000082 eb00100a ADD r0,r0,r10,LSL #4
000086 6831 LDR r1,[r6,#0]
000088 0089 LSLS r1,r1,#2
00008a fbb0f8f1 UDIV r8,r0,r1
|L12.142|
;;;255 }
;;;256 tmpreg = (integerdivider / 100) << 4;
00008e 2064 MOVS r0,#0x64
000090 fbb8f0f0 UDIV r0,r8,r0
000094 0104 LSLS r4,r0,#4
;;;257
;;;258 /* Determine the fractional part */
;;;259 fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
000096 0920 LSRS r0,r4,#4
000098 2164 MOVS r1,#0x64
00009a fb018910 MLS r9,r1,r0,r8
;;;260
;;;261 /* Implement the fractional part in the register */
;;;262 if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
00009e 89a8 LDRH r0,[r5,#0xc]
0000a0 f4104f00 TST r0,#0x8000
0000a4 d008 BEQ |L12.184|
;;;263 {
;;;264 tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
0000a6 2032 MOVS r0,#0x32
0000a8 eb0000c9 ADD r0,r0,r9,LSL #3
0000ac fbb0f0f1 UDIV r0,r0,r1
0000b0 f0000007 AND r0,r0,#7
0000b4 4304 ORRS r4,r4,r0
0000b6 e008 B |L12.202|
|L12.184|
;;;265 }
;;;266 else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
;;;267 {
;;;268 tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
0000b8 2032 MOVS r0,#0x32
0000ba eb001009 ADD r0,r0,r9,LSL #4
0000be 2164 MOVS r1,#0x64
0000c0 fbb0f0f1 UDIV r0,r0,r1
0000c4 f000000f AND r0,r0,#0xf
0000c8 4304 ORRS r4,r4,r0
|L12.202|
;;;269 }
;;;270
;;;271 /* Write to USART BRR */
;;;272 USARTx->BRR = (uint16_t)tmpreg;
0000ca 812c STRH r4,[r5,#8]
;;;273 }
0000cc b006 ADD sp,sp,#0x18
0000ce e8bd87f0 POP {r4-r10,pc}
;;;274
ENDP
0000d2 0000 DCW 0x0000
|L12.212|
DCD 0x40013800
AREA ||i.USART_IrDACmd||, CODE, READONLY, ALIGN=1
USART_IrDACmd PROC
;;;836 */
;;;837 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000 b121 CBZ r1,|L13.12|
;;;838 {
;;;839 /* Check the parameters */
;;;840 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;841 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;842
;;;843 if (NewState != DISABLE)
;;;844 {
;;;845 /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
;;;846 USARTx->CR3 |= CR3_IREN_Set;
000002 8a82 LDRH r2,[r0,#0x14]
000004 f0420202 ORR r2,r2,#2
000008 8282 STRH r2,[r0,#0x14]
00000a e004 B |L13.22|
|L13.12|
;;;847 }
;;;848 else
;;;849 {
;;;850 /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
;;;851 USARTx->CR3 &= CR3_IREN_Reset;
00000c 8a82 LDRH r2,[r0,#0x14]
00000e f64f73fd MOV r3,#0xfffd
000012 401a ANDS r2,r2,r3
000014 8282 STRH r2,[r0,#0x14]
|L13.22|
;;;852 }
;;;853 }
000016 4770 BX lr
;;;854
ENDP
AREA ||i.USART_IrDAConfig||, CODE, READONLY, ALIGN=1
USART_IrDAConfig PROC
;;;817 */
;;;818 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
000000 8a82 LDRH r2,[r0,#0x14]
;;;819 {
;;;820 /* Check the parameters */
;;;821 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;822 assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
;;;823
;;;824 USARTx->CR3 &= CR3_IRLP_Mask;
000002 f64f73fb MOV r3,#0xfffb
000006 401a ANDS r2,r2,r3
000008 8282 STRH r2,[r0,#0x14]
;;;825 USARTx->CR3 |= USART_IrDAMode;
00000a 8a82 LDRH r2,[r0,#0x14]
00000c 430a ORRS r2,r2,r1
00000e 8282 STRH r2,[r0,#0x14]
;;;826 }
000010 4770 BX lr
;;;827
ENDP
AREA ||i.USART_LINBreakDetectLengthConfig||, CODE, READONLY, ALIGN=1
USART_LINBreakDetectLengthConfig PROC
;;;546 */
;;;547 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
000000 8a02 LDRH r2,[r0,#0x10]
;;;548 {
;;;549 /* Check the parameters */
;;;550 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;551 assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
;;;552
;;;553 USARTx->CR2 &= CR2_LBDL_Mask;
000002 f64f73df MOV r3,#0xffdf
000006 401a ANDS r2,r2,r3
000008 8202 STRH r2,[r0,#0x10]
;;;554 USARTx->CR2 |= USART_LINBreakDetectLength;
00000a 8a02 LDRH r2,[r0,#0x10]
00000c 430a ORRS r2,r2,r1
00000e 8202 STRH r2,[r0,#0x10]
;;;555 }
000010 4770 BX lr
;;;556
ENDP
AREA ||i.USART_LINCmd||, CODE, READONLY, ALIGN=1
USART_LINCmd PROC
;;;565 */
;;;566 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000 b121 CBZ r1,|L16.12|
;;;567 {
;;;568 /* Check the parameters */
;;;569 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;570 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;571
;;;572 if (NewState != DISABLE)
;;;573 {
;;;574 /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
;;;575 USARTx->CR2 |= CR2_LINEN_Set;
000002 8a02 LDRH r2,[r0,#0x10]
000004 f4424280 ORR r2,r2,#0x4000
000008 8202 STRH r2,[r0,#0x10]
00000a e004 B |L16.22|
|L16.12|
;;;576 }
;;;577 else
;;;578 {
;;;579 /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
;;;580 USARTx->CR2 &= CR2_LINEN_Reset;
00000c 8a02 LDRH r2,[r0,#0x10]
00000e f64b73ff MOV r3,#0xbfff
000012 401a ANDS r2,r2,r3
000014 8202 STRH r2,[r0,#0x10]
|L16.22|
;;;581 }
;;;582 }
000016 4770 BX lr
;;;583
ENDP
AREA ||i.USART_OneBitMethodCmd||, CODE, READONLY, ALIGN=1
USART_OneBitMethodCmd PROC
;;;788 */
;;;789 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000 b121 CBZ r1,|L17.12|
;;;790 {
;;;791 /* Check the parameters */
;;;792 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;793 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;794
;;;795 if (NewState != DISABLE)
;;;796 {
;;;797 /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
;;;798 USARTx->CR3 |= CR3_ONEBITE_Set;
000002 8a82 LDRH r2,[r0,#0x14]
000004 f4426200 ORR r2,r2,#0x800
000008 8282 STRH r2,[r0,#0x14]
00000a e004 B |L17.22|
|L17.12|
;;;799 }
;;;800 else
;;;801 {
;;;802 /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
;;;803 USARTx->CR3 &= CR3_ONEBITE_Reset;
00000c 8a82 LDRH r2,[r0,#0x14]
00000e f24f73ff MOV r3,#0xf7ff
000012 401a ANDS r2,r2,r3
000014 8282 STRH r2,[r0,#0x14]
|L17.22|
;;;804 }
;;;805 }
000016 4770 BX lr
;;;806
ENDP
AREA ||i.USART_OverSampling8Cmd||, CODE, READONLY, ALIGN=1
USART_OverSampling8Cmd PROC
;;;761 */
;;;762 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000 b121 CBZ r1,|L18.12|
;;;763 {
;;;764 /* Check the parameters */
;;;765 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;766 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;767
;;;768 if (NewState != DISABLE)
;;;769 {
;;;770 /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
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