📄 stm32f10x_rcc.txt
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000006 2300 MOVS r3,#0
;;;1330 FlagStatus bitstatus = RESET;
000008 2000 MOVS r0,#0
;;;1331 /* Check the parameters */
;;;1332 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;1333
;;;1334 /* Get the RCC register index */
;;;1335 tmp = RCC_FLAG >> 5;
00000a 114a ASRS r2,r1,#5
;;;1336 if (tmp == 1) /* The flag to check is in CR register */
00000c 2a01 CMP r2,#1
00000e d102 BNE |L14.22|
;;;1337 {
;;;1338 statusreg = RCC->CR;
000010 4c09 LDR r4,|L14.56|
000012 6823 LDR r3,[r4,#0]
000014 e006 B |L14.36|
|L14.22|
;;;1339 }
;;;1340 else if (tmp == 2) /* The flag to check is in BDCR register */
000016 2a02 CMP r2,#2
000018 d102 BNE |L14.32|
;;;1341 {
;;;1342 statusreg = RCC->BDCR;
00001a 4c07 LDR r4,|L14.56|
00001c 6a23 LDR r3,[r4,#0x20]
00001e e001 B |L14.36|
|L14.32|
;;;1343 }
;;;1344 else /* The flag to check is in CSR register */
;;;1345 {
;;;1346 statusreg = RCC->CSR;
000020 4c05 LDR r4,|L14.56|
000022 6a63 LDR r3,[r4,#0x24]
|L14.36|
;;;1347 }
;;;1348
;;;1349 /* Get the flag position */
;;;1350 tmp = RCC_FLAG & FLAG_Mask;
000024 f001021f AND r2,r1,#0x1f
;;;1351 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
000028 2401 MOVS r4,#1
00002a 4094 LSLS r4,r4,r2
00002c 421c TST r4,r3
00002e d001 BEQ |L14.52|
;;;1352 {
;;;1353 bitstatus = SET;
000030 2001 MOVS r0,#1
000032 e000 B |L14.54|
|L14.52|
;;;1354 }
;;;1355 else
;;;1356 {
;;;1357 bitstatus = RESET;
000034 2000 MOVS r0,#0
|L14.54|
;;;1358 }
;;;1359
;;;1360 /* Return the flag status */
;;;1361 return bitstatus;
;;;1362 }
000036 bd10 POP {r4,pc}
;;;1363
ENDP
|L14.56|
DCD 0x40021000
AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2
RCC_GetITStatus PROC
;;;1401 */
;;;1402 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
000000 4601 MOV r1,r0
;;;1403 {
;;;1404 ITStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;1405 /* Check the parameters */
;;;1406 assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1407
;;;1408 /* Check the status of the specified RCC interrupt */
;;;1409 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
000004 4a03 LDR r2,|L15.20|
000006 6892 LDR r2,[r2,#8]
000008 420a TST r2,r1
00000a d001 BEQ |L15.16|
;;;1410 {
;;;1411 bitstatus = SET;
00000c 2001 MOVS r0,#1
00000e e000 B |L15.18|
|L15.16|
;;;1412 }
;;;1413 else
;;;1414 {
;;;1415 bitstatus = RESET;
000010 2000 MOVS r0,#0
|L15.18|
;;;1416 }
;;;1417
;;;1418 /* Return the RCC_IT status */
;;;1419 return bitstatus;
;;;1420 }
000012 4770 BX lr
;;;1421
ENDP
|L15.20|
DCD 0x40021000
AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2
RCC_GetSYSCLKSource PROC
;;;586 */
;;;587 uint8_t RCC_GetSYSCLKSource(void)
000000 4802 LDR r0,|L16.12|
;;;588 {
;;;589 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
000002 6840 LDR r0,[r0,#4]
000004 f000000c AND r0,r0,#0xc
;;;590 }
000008 4770 BX lr
;;;591
ENDP
00000a 0000 DCW 0x0000
|L16.12|
DCD 0x40021000
AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2
RCC_HCLKConfig PROC
;;;607 */
;;;608 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
000000 4601 MOV r1,r0
;;;609 {
;;;610 uint32_t tmpreg = 0;
000002 2000 MOVS r0,#0
;;;611 /* Check the parameters */
;;;612 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;613 tmpreg = RCC->CFGR;
000004 4a03 LDR r2,|L17.20|
000006 6850 LDR r0,[r2,#4]
;;;614 /* Clear HPRE[3:0] bits */
;;;615 tmpreg &= CFGR_HPRE_Reset_Mask;
000008 f02000f0 BIC r0,r0,#0xf0
;;;616 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;617 tmpreg |= RCC_SYSCLK;
00000c 4308 ORRS r0,r0,r1
;;;618 /* Store the new value */
;;;619 RCC->CFGR = tmpreg;
00000e 6050 STR r0,[r2,#4]
;;;620 }
000010 4770 BX lr
;;;621
ENDP
000012 0000 DCW 0x0000
|L17.20|
DCD 0x40021000
AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2
RCC_HSEConfig PROC
;;;269 */
;;;270 void RCC_HSEConfig(uint32_t RCC_HSE)
000000 4911 LDR r1,|L18.72|
;;;271 {
;;;272 /* Check the parameters */
;;;273 assert_param(IS_RCC_HSE(RCC_HSE));
;;;274 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;275 /* Reset HSEON bit */
;;;276 RCC->CR &= CR_HSEON_Reset;
000002 6809 LDR r1,[r1,#0]
000004 f4213180 BIC r1,r1,#0x10000
000008 4a0f LDR r2,|L18.72|
00000a 6011 STR r1,[r2,#0]
;;;277 /* Reset HSEBYP bit */
;;;278 RCC->CR &= CR_HSEBYP_Reset;
00000c 4611 MOV r1,r2
00000e 6809 LDR r1,[r1,#0]
000010 f4212180 BIC r1,r1,#0x40000
000014 6011 STR r1,[r2,#0]
;;;279 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;280 switch(RCC_HSE)
000016 f5b03f80 CMP r0,#0x10000
00001a d003 BEQ |L18.36|
00001c f5b02f80 CMP r0,#0x40000
000020 d10e BNE |L18.64|
000022 e006 B |L18.50|
|L18.36|
;;;281 {
;;;282 case RCC_HSE_ON:
;;;283 /* Set HSEON bit */
;;;284 RCC->CR |= CR_HSEON_Set;
000024 4908 LDR r1,|L18.72|
000026 6809 LDR r1,[r1,#0]
000028 f4413180 ORR r1,r1,#0x10000
00002c 4a06 LDR r2,|L18.72|
00002e 6011 STR r1,[r2,#0]
;;;285 break;
000030 e007 B |L18.66|
|L18.50|
;;;286
;;;287 case RCC_HSE_Bypass:
;;;288 /* Set HSEBYP and HSEON bits */
;;;289 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
000032 4905 LDR r1,|L18.72|
000034 6809 LDR r1,[r1,#0]
000036 f44121a0 ORR r1,r1,#0x50000
00003a 4a03 LDR r2,|L18.72|
00003c 6011 STR r1,[r2,#0]
;;;290 break;
00003e e000 B |L18.66|
|L18.64|
;;;291
;;;292 default:
;;;293 break;
000040 bf00 NOP
|L18.66|
000042 bf00 NOP ;285
;;;294 }
;;;295 }
000044 4770 BX lr
;;;296
ENDP
000046 0000 DCW 0x0000
|L18.72|
DCD 0x40021000
AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2
RCC_HSICmd PROC
;;;353 */
;;;354 void RCC_HSICmd(FunctionalState NewState)
000000 4901 LDR r1,|L19.8|
;;;355 {
;;;356 /* Check the parameters */
;;;357 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;358 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;359 }
000004 4770 BX lr
;;;360
ENDP
000006 0000 DCW 0x0000
|L19.8|
DCD 0x42420000
AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2
RCC_ITConfig PROC
;;;699 */
;;;700 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
000000 b129 CBZ r1,|L20.14|
;;;701 {
;;;702 /* Check the parameters */
;;;703 assert_param(IS_RCC_IT(RCC_IT));
;;;704 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;705 if (NewState != DISABLE)
;;;706 {
;;;707 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
;;;708 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000002 4a07 LDR r2,|L20.32|
000004 7a52 LDRB r2,[r2,#9]
000006 4302 ORRS r2,r2,r0
000008 4b05 LDR r3,|L20.32|
00000a 725a STRB r2,[r3,#9]
00000c e006 B |L20.28|
|L20.14|
;;;709 }
;;;710 else
;;;711 {
;;;712 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
;;;713 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00000e 4a04 LDR r2,|L20.32|
000010 7a52 LDRB r2,[r2,#9]
000012 43c3 MVNS r3,r0
000014 b2db UXTB r3,r3
000016 401a ANDS r2,r2,r3
000018 4b01 LDR r3,|L20.32|
00001a 725a STRB r2,[r3,#9]
|L20.28|
;;;714 }
;;;715 }
00001c 4770 BX lr
;;;716
ENDP
00001e 0000 DCW 0x0000
|L20.32|
DCD 0x40021000
AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2
RCC_LSEConfig PROC
;;;828 */
;;;829 void RCC_LSEConfig(uint8_t RCC_LSE)
000000 2100 MOVS r1,#0
;;;830 {
;;;831 /* Check the parameters */
;;;832 assert_param(IS_RCC_LSE(RCC_LSE));
;;;833 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;834 /* Reset LSEON bit */
;;;835 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000002 4a0a LDR r2,|L21.44|
000004 7011 STRB r1,[r2,#0]
;;;836 /* Reset LSEBYP bit */
;;;837 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
000006 4a0a LDR r2,|L21.48|
000008 f8821020 STRB r1,[r2,#0x20]
;;;838 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;839 switch(RCC_LSE)
00000c 2801 CMP r0,#1
00000e d002 BEQ |L21.22|
000010 2804 CMP r0,#4
000012 d108 BNE |L21.38|
000014 e003 B |L21.30|
|L21.22|
;;;840 {
;;;841 case RCC_LSE_ON:
;;;842 /* Set LSEON bit */
;;;843 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
000016 2101 MOVS r1,#1
000018 4a04 LDR r2,|L21.44|
00001a 7011 STRB r1,[r2,#0]
;;;844 break;
00001c e004 B |L21.40|
|L21.30|
;;;845
;;;846 case RCC_LSE_Bypass:
;;;847 /* Set LSEBYP and LSEON bits */
;;;848 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00001e 2105 MOVS r1,#5
000020 4a02 LDR r2,|L21.44|
000022 7011 STRB r1,[r2,#0]
;;;849 break;
000024 e000 B |L21.40|
|L21.38|
;;;850
;;;851 default:
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