📄 system_stm32f10x.txt
字号:
000024 4b1b LDR r3,|L3.148|
000026 4c1c LDR r4,|L3.152|
000028 6023 STR r3,[r4,#0] ; SystemCoreClock
;;;328 break;
00002a e023 B |L3.116|
|L3.44|
;;;329 case 0x08: /* PLL used as system clock */
;;;330
;;;331 /* Get PLL clock source and multiplication factor ----------------------*/
;;;332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00002c 4b18 LDR r3,|L3.144|
00002e 685b LDR r3,[r3,#4]
000030 f4031070 AND r0,r3,#0x3c0000
;;;333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
000034 4b16 LDR r3,|L3.144|
000036 685b LDR r3,[r3,#4]
000038 f4033280 AND r2,r3,#0x10000
;;;334
;;;335 #ifndef STM32F10X_CL
;;;336 pllmull = ( pllmull >> 18) + 2;
00003c 2302 MOVS r3,#2
00003e eb034090 ADD r0,r3,r0,LSR #18
;;;337
;;;338 if (pllsource == 0x00)
000042 b922 CBNZ r2,|L3.78|
;;;339 {
;;;340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
000044 4b15 LDR r3,|L3.156|
000046 4343 MULS r3,r0,r3
000048 4c13 LDR r4,|L3.152|
00004a 6023 STR r3,[r4,#0] ; SystemCoreClock
00004c e00d B |L3.106|
|L3.78|
;;;342 }
;;;343 else
;;;344 {
;;;345 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
;;;347 /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
;;;349 #else
;;;350 /* HSE selected as PLL clock entry */
;;;351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
00004e 4b10 LDR r3,|L3.144|
000050 685b LDR r3,[r3,#4]
000052 f4133f00 TST r3,#0x20000
000056 d004 BEQ |L3.98|
;;;352 {/* HSE oscillator clock divided by 2 */
;;;353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
000058 4b10 LDR r3,|L3.156|
00005a 4343 MULS r3,r0,r3
00005c 4c0e LDR r4,|L3.152|
00005e 6023 STR r3,[r4,#0] ; SystemCoreClock
000060 e003 B |L3.106|
|L3.98|
;;;354 }
;;;355 else
;;;356 {
;;;357 SystemCoreClock = HSE_VALUE * pllmull;
000062 4b0c LDR r3,|L3.148|
000064 4343 MULS r3,r0,r3
000066 4c0c LDR r4,|L3.152|
000068 6023 STR r3,[r4,#0] ; SystemCoreClock
|L3.106|
;;;358 }
;;;359 #endif
;;;360 }
;;;361 #else
;;;362 pllmull = pllmull >> 18;
;;;363
;;;364 if (pllmull != 0x0D)
;;;365 {
;;;366 pllmull += 2;
;;;367 }
;;;368 else
;;;369 { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;370 pllmull = 13 / 2;
;;;371 }
;;;372
;;;373 if (pllsource == 0x00)
;;;374 {
;;;375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
;;;377 }
;;;378 else
;;;379 {/* PREDIV1 selected as PLL clock entry */
;;;380
;;;381 /* Get PREDIV1 clock source and division factor */
;;;382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
;;;383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
;;;384
;;;385 if (prediv1source == 0)
;;;386 {
;;;387 /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
;;;389 }
;;;390 else
;;;391 {/* PLL2 clock selected as PREDIV1 clock entry */
;;;392
;;;393 /* Get PREDIV2 division factor and PLL2 multiplication factor */
;;;394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
;;;395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
;;;396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
;;;397 }
;;;398 }
;;;399 #endif /* STM32F10X_CL */
;;;400 break;
00006a e003 B |L3.116|
|L3.108|
;;;401
;;;402 default:
;;;403 SystemCoreClock = HSI_VALUE;
00006c 4b09 LDR r3,|L3.148|
00006e 4c0a LDR r4,|L3.152|
000070 6023 STR r3,[r4,#0] ; SystemCoreClock
;;;404 break;
000072 bf00 NOP
|L3.116|
000074 bf00 NOP ;325
;;;405 }
;;;406
;;;407 /* Compute HCLK clock frequency ----------------*/
;;;408 /* Get HCLK prescaler */
;;;409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
000076 4b06 LDR r3,|L3.144|
000078 685b LDR r3,[r3,#4]
00007a f3c31303 UBFX r3,r3,#4,#4
00007e 4c08 LDR r4,|L3.160|
000080 5ce1 LDRB r1,[r4,r3]
;;;410 /* HCLK clock frequency */
;;;411 SystemCoreClock >>= tmp;
000082 4b05 LDR r3,|L3.152|
000084 681b LDR r3,[r3,#0] ; SystemCoreClock
000086 40cb LSRS r3,r3,r1
000088 4c03 LDR r4,|L3.152|
00008a 6023 STR r3,[r4,#0] ; SystemCoreClock
;;;412 }
00008c bd10 POP {r4,pc}
;;;413
ENDP
00008e 0000 DCW 0x0000
|L3.144|
DCD 0x40021000
|L3.148|
DCD 0x007a1200
|L3.152|
DCD SystemCoreClock
|L3.156|
DCD 0x003d0900
|L3.160|
DCD AHBPrescTable
AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2
SystemInit PROC
;;;211 */
;;;212 void SystemInit (void)
000000 b510 PUSH {r4,lr}
;;;213 {
;;;214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
;;;215 /* Set HSION bit */
;;;216 RCC->CR |= (uint32_t)0x00000001;
000002 4813 LDR r0,|L4.80|
000004 6800 LDR r0,[r0,#0]
000006 f0400001 ORR r0,r0,#1
00000a 4911 LDR r1,|L4.80|
00000c 6008 STR r0,[r1,#0]
;;;217
;;;218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;219 #ifndef STM32F10X_CL
;;;220 RCC->CFGR &= (uint32_t)0xF8FF0000;
00000e 4608 MOV r0,r1
000010 6840 LDR r0,[r0,#4]
000012 4910 LDR r1,|L4.84|
000014 4008 ANDS r0,r0,r1
000016 490e LDR r1,|L4.80|
000018 6048 STR r0,[r1,#4]
;;;221 #else
;;;222 RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;223 #endif /* STM32F10X_CL */
;;;224
;;;225 /* Reset HSEON, CSSON and PLLON bits */
;;;226 RCC->CR &= (uint32_t)0xFEF6FFFF;
00001a 4608 MOV r0,r1
00001c 6800 LDR r0,[r0,#0]
00001e 490e LDR r1,|L4.88|
000020 4008 ANDS r0,r0,r1
000022 490b LDR r1,|L4.80|
000024 6008 STR r0,[r1,#0]
;;;227
;;;228 /* Reset HSEBYP bit */
;;;229 RCC->CR &= (uint32_t)0xFFFBFFFF;
000026 4608 MOV r0,r1
000028 6800 LDR r0,[r0,#0]
00002a f4202080 BIC r0,r0,#0x40000
00002e 6008 STR r0,[r1,#0]
;;;230
;;;231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;232 RCC->CFGR &= (uint32_t)0xFF80FFFF;
000030 4608 MOV r0,r1
000032 6840 LDR r0,[r0,#4]
000034 f42000fe BIC r0,r0,#0x7f0000
000038 6048 STR r0,[r1,#4]
;;;233
;;;234 #ifdef STM32F10X_CL
;;;235 /* Reset PLL2ON and PLL3ON bits */
;;;236 RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;237
;;;238 /* Disable all interrupts and clear pending bits */
;;;239 RCC->CIR = 0x00FF0000;
;;;240
;;;241 /* Reset CFGR2 register */
;;;242 RCC->CFGR2 = 0x00000000;
;;;243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;244 /* Disable all interrupts and clear pending bits */
;;;245 RCC->CIR = 0x009F0000;
;;;246
;;;247 /* Reset CFGR2 register */
;;;248 RCC->CFGR2 = 0x00000000;
;;;249 #else
;;;250 /* Disable all interrupts and clear pending bits */
;;;251 RCC->CIR = 0x009F0000;
00003a f44f001f MOV r0,#0x9f0000
00003e 6088 STR r0,[r1,#8]
;;;252 #endif /* STM32F10X_CL */
;;;253
;;;254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
;;;255 #ifdef DATA_IN_ExtSRAM
;;;256 SystemInit_ExtMemCtl();
;;;257 #endif /* DATA_IN_ExtSRAM */
;;;258 #endif
;;;259
;;;260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
;;;261 /* Configure the Flash Latency cycles and enable prefetch buffer */
;;;262 SetSysClock();
000040 f7fffffe BL SetSysClock
;;;263
;;;264 #ifdef VECT_TAB_SRAM
;;;265 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
000044 f04f5000 MOV r0,#0x20000000
000048 4904 LDR r1,|L4.92|
00004a 6008 STR r0,[r1,#0]
;;;266 #else
;;;267 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
;;;268 #endif
;;;269 }
00004c bd10 POP {r4,pc}
;;;270
ENDP
00004e 0000 DCW 0x0000
|L4.80|
DCD 0x40021000
|L4.84|
DCD 0xf8ff0000
|L4.88|
DCD 0xfef6ffff
|L4.92|
DCD 0xe000ed08
AREA ||.data||, DATA, ALIGN=2
SystemCoreClock
DCD 0x044aa200
AHBPrescTable
000004 00000000 DCB 0x00,0x00,0x00,0x00
000008 00000000 DCB 0x00,0x00,0x00,0x00
00000c 01020304 DCB 0x01,0x02,0x03,0x04
000010 06070809 DCB 0x06,0x07,0x08,0x09
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