📄 system_stm32f10x.txt
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; generated by ARM C/C++ Compiler, 4.1 [Build 561]
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\CpuRAM\Obj\system_stm32f10x.o --depend=.\CpuRAM\Obj\system_stm32f10x.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=870 -I..\..\Libraries\CMSIS\CM3\CoreSupport -I..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\User\bsp -I..\..\User\fatfs -I..\..\User -IC:\Keil\ARM\INC -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER -DVECT_TAB_SRAM ..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c]
THUMB
AREA ||i.SetSysClock||, CODE, READONLY, ALIGN=1
SetSysClock PROC
;;;418 */
;;;419 static void SetSysClock(void)
000000 b510 PUSH {r4,lr}
;;;420 {
;;;421 #ifdef SYSCLK_FREQ_HSE
;;;422 SetSysClockToHSE();
;;;423 #elif defined SYSCLK_FREQ_24MHz
;;;424 SetSysClockTo24();
;;;425 #elif defined SYSCLK_FREQ_36MHz
;;;426 SetSysClockTo36();
;;;427 #elif defined SYSCLK_FREQ_48MHz
;;;428 SetSysClockTo48();
;;;429 #elif defined SYSCLK_FREQ_56MHz
;;;430 SetSysClockTo56();
;;;431 #elif defined SYSCLK_FREQ_72MHz
;;;432 SetSysClockTo72();
000002 f7fffffe BL SetSysClockTo72
;;;433 #endif
;;;434
;;;435 /* If none of the define above is enabled, the HSI is used as System clock
;;;436 source (default after reset) */
;;;437 }
000006 bd10 POP {r4,pc}
;;;438
ENDP
AREA ||i.SetSysClockTo72||, CODE, READONLY, ALIGN=2
SetSysClockTo72 PROC
;;;986 */
;;;987 static void SetSysClockTo72(void)
000000 2100 MOVS r1,#0
;;;988 {
;;;989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002 2000 MOVS r0,#0
;;;990
;;;991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
;;;992 /* Enable HSE */
;;;993 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000004 4a2e LDR r2,|L2.192|
000006 6812 LDR r2,[r2,#0]
000008 f4423280 ORR r2,r2,#0x10000
00000c 4b2c LDR r3,|L2.192|
00000e 601a STR r2,[r3,#0]
;;;994
;;;995 /* Wait till HSE is ready and if Time out is reached exit */
;;;996 do
000010 bf00 NOP
|L2.18|
;;;997 {
;;;998 HSEStatus = RCC->CR & RCC_CR_HSERDY;
000012 4a2b LDR r2,|L2.192|
000014 6812 LDR r2,[r2,#0]
000016 f4023000 AND r0,r2,#0x20000
;;;999 StartUpCounter++;
00001a 1c49 ADDS r1,r1,#1
;;;1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00001c b910 CBNZ r0,|L2.36|
00001e f5b16fa0 CMP r1,#0x500
000022 d1f6 BNE |L2.18|
|L2.36|
;;;1001
;;;1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000024 4a26 LDR r2,|L2.192|
000026 6812 LDR r2,[r2,#0]
000028 f4123f00 TST r2,#0x20000
00002c d001 BEQ |L2.50|
;;;1003 {
;;;1004 HSEStatus = (uint32_t)0x01;
00002e 2001 MOVS r0,#1
000030 e000 B |L2.52|
|L2.50|
;;;1005 }
;;;1006 else
;;;1007 {
;;;1008 HSEStatus = (uint32_t)0x00;
000032 2000 MOVS r0,#0
|L2.52|
;;;1009 }
;;;1010
;;;1011 if (HSEStatus == (uint32_t)0x01)
000034 2801 CMP r0,#1
000036 d142 BNE |L2.190|
;;;1012 {
;;;1013 /* Enable Prefetch Buffer */
;;;1014 FLASH->ACR |= FLASH_ACR_PRFTBE;
000038 4a22 LDR r2,|L2.196|
00003a 6812 LDR r2,[r2,#0]
00003c f0420210 ORR r2,r2,#0x10
000040 4b20 LDR r3,|L2.196|
000042 601a STR r2,[r3,#0]
;;;1015
;;;1016 /* Flash 2 wait state */
;;;1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
000044 461a MOV r2,r3
000046 6812 LDR r2,[r2,#0]
000048 f0220203 BIC r2,r2,#3
00004c 601a STR r2,[r3,#0]
;;;1018 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00004e 461a MOV r2,r3
000050 6812 LDR r2,[r2,#0]
000052 f0420202 ORR r2,r2,#2
000056 601a STR r2,[r3,#0]
;;;1019
;;;1020
;;;1021 /* HCLK = SYSCLK */
;;;1022 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
000058 4a19 LDR r2,|L2.192|
00005a 6852 LDR r2,[r2,#4]
00005c 4b18 LDR r3,|L2.192|
00005e 605a STR r2,[r3,#4]
;;;1023
;;;1024 /* PCLK2 = HCLK */
;;;1025 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
000060 461a MOV r2,r3
000062 6852 LDR r2,[r2,#4]
000064 605a STR r2,[r3,#4]
;;;1026
;;;1027 /* PCLK1 = HCLK */
;;;1028 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
000066 461a MOV r2,r3
000068 6852 LDR r2,[r2,#4]
00006a f4426280 ORR r2,r2,#0x400
00006e 605a STR r2,[r3,#4]
;;;1029
;;;1030 #ifdef STM32F10X_CL
;;;1031 /* Configure PLLs ------------------------------------------------------*/
;;;1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
;;;1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
;;;1034
;;;1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
;;;1036 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
;;;1037 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
;;;1038 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
;;;1039
;;;1040 /* Enable PLL2 */
;;;1041 RCC->CR |= RCC_CR_PLL2ON;
;;;1042 /* Wait till PLL2 is ready */
;;;1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
;;;1044 {
;;;1045 }
;;;1046
;;;1047
;;;1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
;;;1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
;;;1050 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
;;;1051 RCC_CFGR_PLLMULL9);
;;;1052 #else
;;;1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
;;;1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
000070 461a MOV r2,r3
000072 6852 LDR r2,[r2,#4]
000074 f422127c BIC r2,r2,#0x3f0000
000078 605a STR r2,[r3,#4]
;;;1055 RCC_CFGR_PLLMULL));
;;;1056 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
00007a 461a MOV r2,r3
00007c 6852 LDR r2,[r2,#4]
00007e f44212e8 ORR r2,r2,#0x1d0000
000082 605a STR r2,[r3,#4]
;;;1057 #endif /* STM32F10X_CL */
;;;1058
;;;1059 /* Enable PLL */
;;;1060 RCC->CR |= RCC_CR_PLLON;
000084 461a MOV r2,r3
000086 6812 LDR r2,[r2,#0]
000088 f0427280 ORR r2,r2,#0x1000000
00008c 601a STR r2,[r3,#0]
;;;1061
;;;1062 /* Wait till PLL is ready */
;;;1063 while((RCC->CR & RCC_CR_PLLRDY) == 0)
00008e bf00 NOP
|L2.144|
000090 4a0b LDR r2,|L2.192|
000092 6812 LDR r2,[r2,#0]
000094 f0127f00 TST r2,#0x2000000
000098 d0fa BEQ |L2.144|
;;;1064 {
;;;1065 }
;;;1066
;;;1067 /* Select PLL as system clock source */
;;;1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00009a 4a09 LDR r2,|L2.192|
00009c 6852 LDR r2,[r2,#4]
00009e f0220203 BIC r2,r2,#3
0000a2 4b07 LDR r3,|L2.192|
0000a4 605a STR r2,[r3,#4]
;;;1069 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
0000a6 461a MOV r2,r3
0000a8 6852 LDR r2,[r2,#4]
0000aa f0420202 ORR r2,r2,#2
0000ae 605a STR r2,[r3,#4]
;;;1070
;;;1071 /* Wait till PLL is used as system clock source */
;;;1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0000b0 bf00 NOP
|L2.178|
0000b2 4a03 LDR r2,|L2.192|
0000b4 6852 LDR r2,[r2,#4]
0000b6 f002020c AND r2,r2,#0xc
0000ba 2a08 CMP r2,#8
0000bc d1f9 BNE |L2.178|
|L2.190|
;;;1073 {
;;;1074 }
;;;1075 }
;;;1076 else
;;;1077 { /* If HSE fails to start-up, the application will have wrong clock
;;;1078 configuration. User can add here some code to deal with this error */
;;;1079 }
;;;1080 }
0000be 4770 BX lr
;;;1081 #endif
ENDP
|L2.192|
DCD 0x40021000
|L2.196|
DCD 0x40022000
AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2
SystemCoreClockUpdate PROC
;;;305 */
;;;306 void SystemCoreClockUpdate (void)
000000 b510 PUSH {r4,lr}
;;;307 {
;;;308 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
000002 2100 MOVS r1,#0
000004 2000 MOVS r0,#0
000006 2200 MOVS r2,#0
;;;309
;;;310 #ifdef STM32F10X_CL
;;;311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
;;;312 #endif /* STM32F10X_CL */
;;;313
;;;314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
;;;315 uint32_t prediv1factor = 0;
;;;316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
;;;317
;;;318 /* Get SYSCLK source -------------------------------------------------------*/
;;;319 tmp = RCC->CFGR & RCC_CFGR_SWS;
000008 4b21 LDR r3,|L3.144|
00000a 685b LDR r3,[r3,#4]
00000c f003010c AND r1,r3,#0xc
;;;320
;;;321 switch (tmp)
000010 b121 CBZ r1,|L3.28|
000012 2904 CMP r1,#4
000014 d006 BEQ |L3.36|
000016 2908 CMP r1,#8
000018 d128 BNE |L3.108|
00001a e007 B |L3.44|
|L3.28|
;;;322 {
;;;323 case 0x00: /* HSI used as system clock */
;;;324 SystemCoreClock = HSI_VALUE;
00001c 4b1d LDR r3,|L3.148|
00001e 4c1e LDR r4,|L3.152|
000020 6023 STR r3,[r4,#0] ; SystemCoreClock
;;;325 break;
000022 e027 B |L3.116|
|L3.36|
;;;326 case 0x04: /* HSE used as system clock */
;;;327 SystemCoreClock = HSE_VALUE;
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