📄 stm32f10x_dma.txt
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;;;190 }
;;;191 }
00013e 4770 BX lr
;;;192
ENDP
|L4.320|
DCD 0x40020008
|L4.324|
DCD 0x40020408
|L4.328|
DCD 0x40020000
|L4.332|
DCD 0x40020404
AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1
DMA_GetCurrDataCounter PROC
;;;370 */
;;;371 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
000000 4601 MOV r1,r0
;;;372 {
;;;373 /* Check the parameters */
;;;374 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;375 /* Return the number of remaining data units for DMAy Channelx */
;;;376 return ((uint16_t)(DMAy_Channelx->CNDTR));
000002 6848 LDR r0,[r1,#4]
000004 b280 UXTH r0,r0
;;;377 }
000006 4770 BX lr
;;;378
ENDP
AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2
DMA_GetFlagStatus PROC
;;;432 */
;;;433 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
000000 4601 MOV r1,r0
;;;434 {
;;;435 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;436 uint32_t tmpreg = 0;
000004 2200 MOVS r2,#0
;;;437
;;;438 /* Check the parameters */
;;;439 assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
;;;440
;;;441 /* Calculate the used DMAy */
;;;442 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
000006 f0115f80 TST r1,#0x10000000
00000a d002 BEQ |L6.18|
;;;443 {
;;;444 /* Get DMA2 ISR register value */
;;;445 tmpreg = DMA2->ISR ;
00000c 4b05 LDR r3,|L6.36|
00000e 681a LDR r2,[r3,#0]
000010 e001 B |L6.22|
|L6.18|
;;;446 }
;;;447 else
;;;448 {
;;;449 /* Get DMA1 ISR register value */
;;;450 tmpreg = DMA1->ISR ;
000012 4b05 LDR r3,|L6.40|
000014 681a LDR r2,[r3,#0]
|L6.22|
;;;451 }
;;;452
;;;453 /* Check the status of the specified DMAy flag */
;;;454 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
000016 420a TST r2,r1
000018 d001 BEQ |L6.30|
;;;455 {
;;;456 /* DMAy_FLAG is set */
;;;457 bitstatus = SET;
00001a 2001 MOVS r0,#1
00001c e000 B |L6.32|
|L6.30|
;;;458 }
;;;459 else
;;;460 {
;;;461 /* DMAy_FLAG is reset */
;;;462 bitstatus = RESET;
00001e 2000 MOVS r0,#0
|L6.32|
;;;463 }
;;;464
;;;465 /* Return the DMAy_FLAG status */
;;;466 return bitstatus;
;;;467 }
000020 4770 BX lr
;;;468
ENDP
000022 0000 DCW 0x0000
|L6.36|
DCD 0x40020400
|L6.40|
DCD 0x40020000
AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2
DMA_GetITStatus PROC
;;;594 */
;;;595 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
000000 4601 MOV r1,r0
;;;596 {
;;;597 ITStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;598 uint32_t tmpreg = 0;
000004 2200 MOVS r2,#0
;;;599
;;;600 /* Check the parameters */
;;;601 assert_param(IS_DMA_GET_IT(DMAy_IT));
;;;602
;;;603 /* Calculate the used DMA */
;;;604 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
000006 f0115f80 TST r1,#0x10000000
00000a d002 BEQ |L7.18|
;;;605 {
;;;606 /* Get DMA2 ISR register value */
;;;607 tmpreg = DMA2->ISR;
00000c 4b05 LDR r3,|L7.36|
00000e 681a LDR r2,[r3,#0]
000010 e001 B |L7.22|
|L7.18|
;;;608 }
;;;609 else
;;;610 {
;;;611 /* Get DMA1 ISR register value */
;;;612 tmpreg = DMA1->ISR;
000012 4b05 LDR r3,|L7.40|
000014 681a LDR r2,[r3,#0]
|L7.22|
;;;613 }
;;;614
;;;615 /* Check the status of the specified DMAy interrupt */
;;;616 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
000016 420a TST r2,r1
000018 d001 BEQ |L7.30|
;;;617 {
;;;618 /* DMAy_IT is set */
;;;619 bitstatus = SET;
00001a 2001 MOVS r0,#1
00001c e000 B |L7.32|
|L7.30|
;;;620 }
;;;621 else
;;;622 {
;;;623 /* DMAy_IT is reset */
;;;624 bitstatus = RESET;
00001e 2000 MOVS r0,#0
|L7.32|
;;;625 }
;;;626 /* Return the DMA_IT status */
;;;627 return bitstatus;
;;;628 }
000020 4770 BX lr
;;;629
ENDP
000022 0000 DCW 0x0000
|L7.36|
DCD 0x40020400
|L7.40|
DCD 0x40020000
AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1
DMA_ITConfig PROC
;;;325 */
;;;326 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
000000 b11a CBZ r2,|L8.10|
;;;327 {
;;;328 /* Check the parameters */
;;;329 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;330 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;331 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;332 if (NewState != DISABLE)
;;;333 {
;;;334 /* Enable the selected DMA interrupts */
;;;335 DMAy_Channelx->CCR |= DMA_IT;
000002 6803 LDR r3,[r0,#0]
000004 430b ORRS r3,r3,r1
000006 6003 STR r3,[r0,#0]
000008 e002 B |L8.16|
|L8.10|
;;;336 }
;;;337 else
;;;338 {
;;;339 /* Disable the selected DMA interrupts */
;;;340 DMAy_Channelx->CCR &= ~DMA_IT;
00000a 6803 LDR r3,[r0,#0]
00000c 438b BICS r3,r3,r1
00000e 6003 STR r3,[r0,#0]
|L8.16|
;;;341 }
;;;342 }
000010 4770 BX lr
;;;343
ENDP
AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1
DMA_Init PROC
;;;201 */
;;;202 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
000000 b510 PUSH {r4,lr}
;;;203 {
;;;204 uint32_t tmpreg = 0;
000002 2200 MOVS r2,#0
;;;205
;;;206 /* Check the parameters */
;;;207 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;208 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;209 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;210 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;211 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
;;;212 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;213 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;214 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;215 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;216 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;217
;;;218 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
;;;219 /* Get the DMAy_Channelx CCR value */
;;;220 tmpreg = DMAy_Channelx->CCR;
000004 6802 LDR r2,[r0,#0]
;;;221 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;222 tmpreg &= CCR_CLEAR_Mask;
000006 f64773f0 MOV r3,#0x7ff0
00000a 439a BICS r2,r2,r3
;;;223 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
;;;224 /* Set DIR bit according to DMA_DIR value */
;;;225 /* Set CIRC bit according to DMA_Mode value */
;;;226 /* Set PINC bit according to DMA_PeripheralInc value */
;;;227 /* Set MINC bit according to DMA_MemoryInc value */
;;;228 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;229 /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;230 /* Set PL bits according to DMA_Priority value */
;;;231 /* Set the MEM2MEM bit according to DMA_M2M value */
;;;232 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00000c 6a0c LDR r4,[r1,#0x20]
00000e 688b LDR r3,[r1,#8]
000010 4323 ORRS r3,r3,r4
000012 690c LDR r4,[r1,#0x10]
000014 4323 ORRS r3,r3,r4
000016 694c LDR r4,[r1,#0x14]
000018 4323 ORRS r3,r3,r4
00001a 698c LDR r4,[r1,#0x18]
00001c 4323 ORRS r3,r3,r4
00001e 69cc LDR r4,[r1,#0x1c]
000020 4323 ORRS r3,r3,r4
000022 6a4c LDR r4,[r1,#0x24]
000024 4323 ORRS r3,r3,r4
000026 6a8c LDR r4,[r1,#0x28]
000028 4323 ORRS r3,r3,r4
00002a 431a ORRS r2,r2,r3
;;;233 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;234 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;235 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;236
;;;237 /* Write to DMAy Channelx CCR */
;;;238 DMAy_Channelx->CCR = tmpreg;
00002c 6002 STR r2,[r0,#0]
;;;239
;;;240 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;241 /* Write to DMAy Channelx CNDTR */
;;;242 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00002e 68cb LDR r3,[r1,#0xc]
000030 6043 STR r3,[r0,#4]
;;;243
;;;244 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
;;;245 /* Write to DMAy Channelx CPAR */
;;;246 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000032 680b LDR r3,[r1,#0]
000034 6083 STR r3,[r0,#8]
;;;247
;;;248 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
;;;249 /* Write to DMAy Channelx CMAR */
;;;250 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
000036 684b LDR r3,[r1,#4]
000038 60c3 STR r3,[r0,#0xc]
;;;251 }
00003a bd10 POP {r4,pc}
;;;252
ENDP
AREA ||i.DMA_SetCurrDataCounter||, CODE, READONLY, ALIGN=1
DMA_SetCurrDataCounter PROC
;;;352 */
;;;353 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
000000 6041 STR r1,[r0,#4]
;;;354 {
;;;355 /* Check the parameters */
;;;356 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;357
;;;358 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;359 /* Write to DMAy Channelx CNDTR */
;;;360 DMAy_Channelx->CNDTR = DataNumber;
;;;361 }
000002 4770 BX lr
;;;362
ENDP
AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1
DMA_StructInit PROC
;;;258 */
;;;259 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000 2100 MOVS r1,#0
;;;260 {
;;;261 /*-------------- Reset DMA init structure parameters values ------------------*/
;;;262 /* Initialize the DMA_PeripheralBaseAddr member */
;;;263 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
000002 6001 STR r1,[r0,#0]
;;;264 /* Initialize the DMA_MemoryBaseAddr member */
;;;265 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
000004 6041 STR r1,[r0,#4]
;;;266 /* Initialize the DMA_DIR member */
;;;267 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
000006 6081 STR r1,[r0,#8]
;;;268 /* Initialize the DMA_BufferSize member */
;;;269 DMA_InitStruct->DMA_BufferSize = 0;
000008 60c1 STR r1,[r0,#0xc]
;;;270 /* Initialize the DMA_PeripheralInc member */
;;;271 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
00000a 6101 STR r1,[r0,#0x10]
;;;272 /* Initialize the DMA_MemoryInc member */
;;;273 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000c 6141 STR r1,[r0,#0x14]
;;;274 /* Initialize the DMA_PeripheralDataSize member */
;;;275 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00000e 6181 STR r1,[r0,#0x18]
;;;276 /* Initialize the DMA_MemoryDataSize member */
;;;277 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
000010 61c1 STR r1,[r0,#0x1c]
;;;278 /* Initialize the DMA_Mode member */
;;;279 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000012 6201 STR r1,[r0,#0x20]
;;;280 /* Initialize the DMA_Priority member */
;;;281 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000014 6241 STR r1,[r0,#0x24]
;;;282 /* Initialize the DMA_M2M member */
;;;283 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
000016 6281 STR r1,[r0,#0x28]
;;;284 }
000018 4770 BX lr
;;;285
ENDP
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