📄 stm32f10x_dma.txt
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; generated by ARM C/C++ Compiler, 4.1 [Build 561]
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Flash\Obj\stm32f10x_dma.o --depend=.\Flash\Obj\stm32f10x_dma.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=870 -I..\..\Libraries\CMSIS\CM3\CoreSupport -I..\..\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\User\bsp -I..\..\User\fatfs -I..\..\User -IC:\Keil\ARM\INC -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c]
THUMB
AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2
DMA_ClearFlag PROC
;;;522 */
;;;523 void DMA_ClearFlag(uint32_t DMAy_FLAG)
000000 f0105f80 TST r0,#0x10000000
;;;524 {
;;;525 /* Check the parameters */
;;;526 assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
;;;527
;;;528 /* Calculate the used DMAy */
;;;529 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
000004 d002 BEQ |L1.12|
;;;530 {
;;;531 /* Clear the selected DMAy flags */
;;;532 DMA2->IFCR = DMAy_FLAG;
000006 4903 LDR r1,|L1.20|
000008 6008 STR r0,[r1,#0]
00000a e001 B |L1.16|
|L1.12|
;;;533 }
;;;534 else
;;;535 {
;;;536 /* Clear the selected DMAy flags */
;;;537 DMA1->IFCR = DMAy_FLAG;
00000c 4902 LDR r1,|L1.24|
00000e 6048 STR r0,[r1,#4]
|L1.16|
;;;538 }
;;;539 }
000010 4770 BX lr
;;;540
ENDP
000012 0000 DCW 0x0000
|L1.20|
DCD 0x40020404
|L1.24|
DCD 0x40020000
AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2
DMA_ClearITPendingBit PROC
;;;683 */
;;;684 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
000000 f0105f80 TST r0,#0x10000000
;;;685 {
;;;686 /* Check the parameters */
;;;687 assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
;;;688
;;;689 /* Calculate the used DMAy */
;;;690 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
000004 d002 BEQ |L2.12|
;;;691 {
;;;692 /* Clear the selected DMAy interrupt pending bits */
;;;693 DMA2->IFCR = DMAy_IT;
000006 4903 LDR r1,|L2.20|
000008 6008 STR r0,[r1,#0]
00000a e001 B |L2.16|
|L2.12|
;;;694 }
;;;695 else
;;;696 {
;;;697 /* Clear the selected DMAy interrupt pending bits */
;;;698 DMA1->IFCR = DMAy_IT;
00000c 4902 LDR r1,|L2.24|
00000e 6048 STR r0,[r1,#4]
|L2.16|
;;;699 }
;;;700 }
000010 4770 BX lr
;;;701
ENDP
000012 0000 DCW 0x0000
|L2.20|
DCD 0x40020404
|L2.24|
DCD 0x40020000
AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1
DMA_Cmd PROC
;;;293 */
;;;294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
000000 b121 CBZ r1,|L3.12|
;;;295 {
;;;296 /* Check the parameters */
;;;297 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;298 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;299
;;;300 if (NewState != DISABLE)
;;;301 {
;;;302 /* Enable the selected DMAy Channelx */
;;;303 DMAy_Channelx->CCR |= DMA_CCR1_EN;
000002 6802 LDR r2,[r0,#0]
000004 f0420201 ORR r2,r2,#1
000008 6002 STR r2,[r0,#0]
00000a e004 B |L3.22|
|L3.12|
;;;304 }
;;;305 else
;;;306 {
;;;307 /* Disable the selected DMAy Channelx */
;;;308 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
00000c 6802 LDR r2,[r0,#0]
00000e f64f73fe MOV r3,#0xfffe
000012 401a ANDS r2,r2,r3
000014 6002 STR r2,[r0,#0]
|L3.22|
;;;309 }
;;;310 }
000016 4770 BX lr
;;;311
ENDP
AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2
DMA_DeInit PROC
;;;107 */
;;;108 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
000000 6801 LDR r1,[r0,#0]
;;;109 {
;;;110 /* Check the parameters */
;;;111 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;112
;;;113 /* Disable the selected DMAy Channelx */
;;;114 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
000002 f64f72fe MOV r2,#0xfffe
000006 4011 ANDS r1,r1,r2
000008 6001 STR r1,[r0,#0]
;;;115
;;;116 /* Reset DMAy Channelx control register */
;;;117 DMAy_Channelx->CCR = 0;
00000a 2100 MOVS r1,#0
00000c 6001 STR r1,[r0,#0]
;;;118
;;;119 /* Reset DMAy Channelx remaining bytes register */
;;;120 DMAy_Channelx->CNDTR = 0;
00000e 6041 STR r1,[r0,#4]
;;;121
;;;122 /* Reset DMAy Channelx peripheral address register */
;;;123 DMAy_Channelx->CPAR = 0;
000010 6081 STR r1,[r0,#8]
;;;124
;;;125 /* Reset DMAy Channelx memory address register */
;;;126 DMAy_Channelx->CMAR = 0;
000012 60c1 STR r1,[r0,#0xc]
;;;127
;;;128 if (DMAy_Channelx == DMA1_Channel1)
000014 494a LDR r1,|L4.320|
000016 4288 CMP r0,r1
000018 d108 BNE |L4.44|
;;;129 {
;;;130 /* Reset interrupt pending bits for DMA1 Channel1 */
;;;131 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
00001a 4949 LDR r1,|L4.320|
00001c 3908 SUBS r1,r1,#8
00001e 6849 LDR r1,[r1,#4]
000020 f041010f ORR r1,r1,#0xf
000024 4a46 LDR r2,|L4.320|
000026 3a08 SUBS r2,r2,#8
000028 6051 STR r1,[r2,#4]
00002a e088 B |L4.318|
|L4.44|
;;;132 }
;;;133 else if (DMAy_Channelx == DMA1_Channel2)
00002c 4944 LDR r1,|L4.320|
00002e 3114 ADDS r1,r1,#0x14
000030 4288 CMP r0,r1
000032 d108 BNE |L4.70|
;;;134 {
;;;135 /* Reset interrupt pending bits for DMA1 Channel2 */
;;;136 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
000034 4942 LDR r1,|L4.320|
000036 3908 SUBS r1,r1,#8
000038 6849 LDR r1,[r1,#4]
00003a f04101f0 ORR r1,r1,#0xf0
00003e 4a40 LDR r2,|L4.320|
000040 3a08 SUBS r2,r2,#8
000042 6051 STR r1,[r2,#4]
000044 e07b B |L4.318|
|L4.70|
;;;137 }
;;;138 else if (DMAy_Channelx == DMA1_Channel3)
000046 493e LDR r1,|L4.320|
000048 3128 ADDS r1,r1,#0x28
00004a 4288 CMP r0,r1
00004c d108 BNE |L4.96|
;;;139 {
;;;140 /* Reset interrupt pending bits for DMA1 Channel3 */
;;;141 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00004e 493c LDR r1,|L4.320|
000050 3908 SUBS r1,r1,#8
000052 6849 LDR r1,[r1,#4]
000054 f4416170 ORR r1,r1,#0xf00
000058 4a39 LDR r2,|L4.320|
00005a 3a08 SUBS r2,r2,#8
00005c 6051 STR r1,[r2,#4]
00005e e06e B |L4.318|
|L4.96|
;;;142 }
;;;143 else if (DMAy_Channelx == DMA1_Channel4)
000060 4937 LDR r1,|L4.320|
000062 313c ADDS r1,r1,#0x3c
000064 4288 CMP r0,r1
000066 d108 BNE |L4.122|
;;;144 {
;;;145 /* Reset interrupt pending bits for DMA1 Channel4 */
;;;146 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
000068 4935 LDR r1,|L4.320|
00006a 3908 SUBS r1,r1,#8
00006c 6849 LDR r1,[r1,#4]
00006e f4414170 ORR r1,r1,#0xf000
000072 4a33 LDR r2,|L4.320|
000074 3a08 SUBS r2,r2,#8
000076 6051 STR r1,[r2,#4]
000078 e061 B |L4.318|
|L4.122|
;;;147 }
;;;148 else if (DMAy_Channelx == DMA1_Channel5)
00007a 4931 LDR r1,|L4.320|
00007c 3150 ADDS r1,r1,#0x50
00007e 4288 CMP r0,r1
000080 d108 BNE |L4.148|
;;;149 {
;;;150 /* Reset interrupt pending bits for DMA1 Channel5 */
;;;151 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
000082 492f LDR r1,|L4.320|
000084 3908 SUBS r1,r1,#8
000086 6849 LDR r1,[r1,#4]
000088 f4412170 ORR r1,r1,#0xf0000
00008c 4a2c LDR r2,|L4.320|
00008e 3a08 SUBS r2,r2,#8
000090 6051 STR r1,[r2,#4]
000092 e054 B |L4.318|
|L4.148|
;;;152 }
;;;153 else if (DMAy_Channelx == DMA1_Channel6)
000094 492a LDR r1,|L4.320|
000096 3164 ADDS r1,r1,#0x64
000098 4288 CMP r0,r1
00009a d108 BNE |L4.174|
;;;154 {
;;;155 /* Reset interrupt pending bits for DMA1 Channel6 */
;;;156 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00009c 4928 LDR r1,|L4.320|
00009e 3908 SUBS r1,r1,#8
0000a0 6849 LDR r1,[r1,#4]
0000a2 f4410170 ORR r1,r1,#0xf00000
0000a6 4a26 LDR r2,|L4.320|
0000a8 3a08 SUBS r2,r2,#8
0000aa 6051 STR r1,[r2,#4]
0000ac e047 B |L4.318|
|L4.174|
;;;157 }
;;;158 else if (DMAy_Channelx == DMA1_Channel7)
0000ae 4924 LDR r1,|L4.320|
0000b0 3178 ADDS r1,r1,#0x78
0000b2 4288 CMP r0,r1
0000b4 d108 BNE |L4.200|
;;;159 {
;;;160 /* Reset interrupt pending bits for DMA1 Channel7 */
;;;161 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
0000b6 4922 LDR r1,|L4.320|
0000b8 3908 SUBS r1,r1,#8
0000ba 6849 LDR r1,[r1,#4]
0000bc f0416170 ORR r1,r1,#0xf000000
0000c0 4a1f LDR r2,|L4.320|
0000c2 3a08 SUBS r2,r2,#8
0000c4 6051 STR r1,[r2,#4]
0000c6 e03a B |L4.318|
|L4.200|
;;;162 }
;;;163 else if (DMAy_Channelx == DMA2_Channel1)
0000c8 491e LDR r1,|L4.324|
0000ca 4288 CMP r0,r1
0000cc d108 BNE |L4.224|
;;;164 {
;;;165 /* Reset interrupt pending bits for DMA2 Channel1 */
;;;166 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
0000ce f1a00104 SUB r1,r0,#4
0000d2 6809 LDR r1,[r1,#0]
0000d4 f041010f ORR r1,r1,#0xf
0000d8 4a1b LDR r2,|L4.328|
0000da f8c21404 STR r1,[r2,#0x404]
0000de e02e B |L4.318|
|L4.224|
;;;167 }
;;;168 else if (DMAy_Channelx == DMA2_Channel2)
0000e0 4918 LDR r1,|L4.324|
0000e2 3114 ADDS r1,r1,#0x14
0000e4 4288 CMP r0,r1
0000e6 d107 BNE |L4.248|
;;;169 {
;;;170 /* Reset interrupt pending bits for DMA2 Channel2 */
;;;171 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
0000e8 4918 LDR r1,|L4.332|
0000ea 6809 LDR r1,[r1,#0]
0000ec f04101f0 ORR r1,r1,#0xf0
0000f0 4a15 LDR r2,|L4.328|
0000f2 f8c21404 STR r1,[r2,#0x404]
0000f6 e022 B |L4.318|
|L4.248|
;;;172 }
;;;173 else if (DMAy_Channelx == DMA2_Channel3)
0000f8 4912 LDR r1,|L4.324|
0000fa 3128 ADDS r1,r1,#0x28
0000fc 4288 CMP r0,r1
0000fe d107 BNE |L4.272|
;;;174 {
;;;175 /* Reset interrupt pending bits for DMA2 Channel3 */
;;;176 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
000100 4912 LDR r1,|L4.332|
000102 6809 LDR r1,[r1,#0]
000104 f4416170 ORR r1,r1,#0xf00
000108 4a0f LDR r2,|L4.328|
00010a f8c21404 STR r1,[r2,#0x404]
00010e e016 B |L4.318|
|L4.272|
;;;177 }
;;;178 else if (DMAy_Channelx == DMA2_Channel4)
000110 490c LDR r1,|L4.324|
000112 313c ADDS r1,r1,#0x3c
000114 4288 CMP r0,r1
000116 d107 BNE |L4.296|
;;;179 {
;;;180 /* Reset interrupt pending bits for DMA2 Channel4 */
;;;181 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
000118 490c LDR r1,|L4.332|
00011a 6809 LDR r1,[r1,#0]
00011c f4414170 ORR r1,r1,#0xf000
000120 4a09 LDR r2,|L4.328|
000122 f8c21404 STR r1,[r2,#0x404]
000126 e00a B |L4.318|
|L4.296|
;;;182 }
;;;183 else
;;;184 {
;;;185 if (DMAy_Channelx == DMA2_Channel5)
000128 4906 LDR r1,|L4.324|
00012a 3150 ADDS r1,r1,#0x50
00012c 4288 CMP r0,r1
00012e d106 BNE |L4.318|
;;;186 {
;;;187 /* Reset interrupt pending bits for DMA2 Channel5 */
;;;188 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
000130 4906 LDR r1,|L4.332|
000132 6809 LDR r1,[r1,#0]
000134 f4412170 ORR r1,r1,#0xf0000
000138 4a03 LDR r2,|L4.328|
00013a f8c21404 STR r1,[r2,#0x404]
|L4.318|
;;;189 }
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