📄 stm32f10x_rcc.txt
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;;;1254 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
000002 64c8 STR r0,[r1,#0x4c]
;;;1255 }
000004 4770 BX lr
;;;1256
ENDP
000006 0000 DCW 0x0000
|L11.8|
DCD 0x42420000
AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;216 */
;;;217 void RCC_DeInit(void)
000000 480f LDR r0,|L12.64|
;;;218 {
;;;219 /* Set HSION bit */
;;;220 RCC->CR |= (uint32_t)0x00000001;
000002 6800 LDR r0,[r0,#0]
000004 f0400001 ORR r0,r0,#1
000008 490d LDR r1,|L12.64|
00000a 6008 STR r0,[r1,#0]
;;;221
;;;222 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;223 #ifndef STM32F10X_CL
;;;224 RCC->CFGR &= (uint32_t)0xF8FF0000;
00000c 4608 MOV r0,r1
00000e 6840 LDR r0,[r0,#4]
000010 490c LDR r1,|L12.68|
000012 4008 ANDS r0,r0,r1
000014 490a LDR r1,|L12.64|
000016 6048 STR r0,[r1,#4]
;;;225 #else
;;;226 RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;227 #endif /* STM32F10X_CL */
;;;228
;;;229 /* Reset HSEON, CSSON and PLLON bits */
;;;230 RCC->CR &= (uint32_t)0xFEF6FFFF;
000018 4608 MOV r0,r1
00001a 6800 LDR r0,[r0,#0]
00001c 490a LDR r1,|L12.72|
00001e 4008 ANDS r0,r0,r1
000020 4907 LDR r1,|L12.64|
000022 6008 STR r0,[r1,#0]
;;;231
;;;232 /* Reset HSEBYP bit */
;;;233 RCC->CR &= (uint32_t)0xFFFBFFFF;
000024 4608 MOV r0,r1
000026 6800 LDR r0,[r0,#0]
000028 f4202080 BIC r0,r0,#0x40000
00002c 6008 STR r0,[r1,#0]
;;;234
;;;235 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;236 RCC->CFGR &= (uint32_t)0xFF80FFFF;
00002e 4608 MOV r0,r1
000030 6840 LDR r0,[r0,#4]
000032 f42000fe BIC r0,r0,#0x7f0000
000036 6048 STR r0,[r1,#4]
;;;237
;;;238 #ifdef STM32F10X_CL
;;;239 /* Reset PLL2ON and PLL3ON bits */
;;;240 RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;241
;;;242 /* Disable all interrupts and clear pending bits */
;;;243 RCC->CIR = 0x00FF0000;
;;;244
;;;245 /* Reset CFGR2 register */
;;;246 RCC->CFGR2 = 0x00000000;
;;;247 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;248 /* Disable all interrupts and clear pending bits */
;;;249 RCC->CIR = 0x009F0000;
;;;250
;;;251 /* Reset CFGR2 register */
;;;252 RCC->CFGR2 = 0x00000000;
;;;253 #else
;;;254 /* Disable all interrupts and clear pending bits */
;;;255 RCC->CIR = 0x009F0000;
000038 f44f001f MOV r0,#0x9f0000
00003c 6088 STR r0,[r1,#8]
;;;256 #endif /* STM32F10X_CL */
;;;257
;;;258 }
00003e 4770 BX lr
;;;259
ENDP
|L12.64|
DCD 0x40021000
|L12.68|
DCD 0xf8ff0000
|L12.72|
DCD 0xfef6ffff
AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2
RCC_GetClocksFreq PROC
;;;907 */
;;;908 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000 b530 PUSH {r4,r5,lr}
;;;909 {
;;;910 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
000002 2100 MOVS r1,#0
000004 2200 MOVS r2,#0
000006 2400 MOVS r4,#0
000008 2300 MOVS r3,#0
;;;911
;;;912 #ifdef STM32F10X_CL
;;;913 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
;;;914 #endif /* STM32F10X_CL */
;;;915
;;;916 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;917 uint32_t prediv1factor = 0;
;;;918 #endif
;;;919
;;;920 /* Get SYSCLK source -------------------------------------------------------*/
;;;921 tmp = RCC->CFGR & CFGR_SWS_Mask;
00000a 4d2d LDR r5,|L13.192|
00000c 686d LDR r5,[r5,#4]
00000e f005010c AND r1,r5,#0xc
;;;922
;;;923 switch (tmp)
000012 b121 CBZ r1,|L13.30|
000014 2904 CMP r1,#4
000016 d005 BEQ |L13.36|
000018 2908 CMP r1,#8
00001a d123 BNE |L13.100|
00001c e005 B |L13.42|
|L13.30|
;;;924 {
;;;925 case 0x00: /* HSI used as system clock */
;;;926 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00001e 4d29 LDR r5,|L13.196|
000020 6005 STR r5,[r0,#0]
;;;927 break;
000022 e022 B |L13.106|
|L13.36|
;;;928 case 0x04: /* HSE used as system clock */
;;;929 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
000024 4d27 LDR r5,|L13.196|
000026 6005 STR r5,[r0,#0]
;;;930 break;
000028 e01f B |L13.106|
|L13.42|
;;;931 case 0x08: /* PLL used as system clock */
;;;932
;;;933 /* Get PLL clock source and multiplication factor ----------------------*/
;;;934 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00002a 4d25 LDR r5,|L13.192|
00002c 686d LDR r5,[r5,#4]
00002e f4051270 AND r2,r5,#0x3c0000
;;;935 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000032 4d23 LDR r5,|L13.192|
000034 686d LDR r5,[r5,#4]
000036 f4053480 AND r4,r5,#0x10000
;;;936
;;;937 #ifndef STM32F10X_CL
;;;938 pllmull = ( pllmull >> 18) + 2;
00003a 2502 MOVS r5,#2
00003c eb054292 ADD r2,r5,r2,LSR #18
;;;939
;;;940 if (pllsource == 0x00)
000040 b91c CBNZ r4,|L13.74|
;;;941 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;942 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
000042 4d21 LDR r5,|L13.200|
000044 4355 MULS r5,r2,r5
000046 6005 STR r5,[r0,#0]
000048 e00b B |L13.98|
|L13.74|
;;;943 }
;;;944 else
;;;945 {
;;;946 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;947 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;948 /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;949 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
;;;950 #else
;;;951 /* HSE selected as PLL clock entry */
;;;952 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00004a 4d1d LDR r5,|L13.192|
00004c 686d LDR r5,[r5,#4]
00004e f4153f00 TST r5,#0x20000
000052 d003 BEQ |L13.92|
;;;953 {/* HSE oscillator clock divided by 2 */
;;;954 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
000054 4d1c LDR r5,|L13.200|
000056 4355 MULS r5,r2,r5
000058 6005 STR r5,[r0,#0]
00005a e002 B |L13.98|
|L13.92|
;;;955 }
;;;956 else
;;;957 {
;;;958 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00005c 4d19 LDR r5,|L13.196|
00005e 4355 MULS r5,r2,r5
000060 6005 STR r5,[r0,#0]
|L13.98|
;;;959 }
;;;960 #endif
;;;961 }
;;;962 #else
;;;963 pllmull = pllmull >> 18;
;;;964
;;;965 if (pllmull != 0x0D)
;;;966 {
;;;967 pllmull += 2;
;;;968 }
;;;969 else
;;;970 { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;971 pllmull = 13 / 2;
;;;972 }
;;;973
;;;974 if (pllsource == 0x00)
;;;975 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;976 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
;;;977 }
;;;978 else
;;;979 {/* PREDIV1 selected as PLL clock entry */
;;;980
;;;981 /* Get PREDIV1 clock source and division factor */
;;;982 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
;;;983 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;984
;;;985 if (prediv1source == 0)
;;;986 { /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;987 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
;;;988 }
;;;989 else
;;;990 {/* PLL2 clock selected as PREDIV1 clock entry */
;;;991
;;;992 /* Get PREDIV2 division factor and PLL2 multiplication factor */
;;;993 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
;;;994 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
;;;995 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
;;;996 }
;;;997 }
;;;998 #endif /* STM32F10X_CL */
;;;999 break;
000062 e002 B |L13.106|
|L13.100|
;;;1000
;;;1001 default:
;;;1002 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
000064 4d17 LDR r5,|L13.196|
000066 6005 STR r5,[r0,#0]
;;;1003 break;
000068 bf00 NOP
|L13.106|
00006a bf00 NOP ;927
;;;1004 }
;;;1005
;;;1006 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;1007 /* Get HCLK prescaler */
;;;1008 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00006c 4d14 LDR r5,|L13.192|
00006e 686d LDR r5,[r5,#4]
000070 f00501f0 AND r1,r5,#0xf0
;;;1009 tmp = tmp >> 4;
000074 0909 LSRS r1,r1,#4
;;;1010 presc = APBAHBPrescTable[tmp];
000076 4d15 LDR r5,|L13.204|
000078 5c6b LDRB r3,[r5,r1]
;;;1011 /* HCLK clock frequency */
;;;1012 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00007a 6805 LDR r5,[r0,#0]
00007c 40dd LSRS r5,r5,r3
00007e 6045 STR r5,[r0,#4]
;;;1013 /* Get PCLK1 prescaler */
;;;1014 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000080 4d0f LDR r5,|L13.192|
000082 686d LDR r5,[r5,#4]
000084 f40561e0 AND r1,r5,#0x700
;;;1015 tmp = tmp >> 8;
000088 0a09 LSRS r1,r1,#8
;;;1016 presc = APBAHBPrescTable[tmp];
00008a 4d10 LDR r5,|L13.204|
00008c 5c6b LDRB r3,[r5,r1]
;;;1017 /* PCLK1 clock frequency */
;;;1018 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00008e 6845 LDR r5,[r0,#4]
000090 40dd LSRS r5,r5,r3
000092 6085 STR r5,[r0,#8]
;;;1019 /* Get PCLK2 prescaler */
;;;1020 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000094 4d0a LDR r5,|L13.192|
000096 686d LDR r5,[r5,#4]
000098 f4055160 AND r1,r5,#0x3800
;;;1021 tmp = tmp >> 11;
00009c 0ac9 LSRS r1,r1,#11
;;;1022 presc = APBAHBPrescTable[tmp];
00009e 4d0b LDR r5,|L13.204|
0000a0 5c6b LDRB r3,[r5,r1]
;;;1023 /* PCLK2 clock frequency */
;;;1024 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0000a2 6845 LDR r5,[r0,#4]
0000a4 40dd LSRS r5,r5,r3
0000a6 60c5 STR r5,[r0,#0xc]
;;;1025 /* Get ADCCLK prescaler */
;;;1026 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
0000a8 4d05 LDR r5,|L13.192|
0000aa 686d LDR r5,[r5,#4]
0000ac f4054140 AND r1,r5,#0xc000
;;;1027 tmp = tmp >> 14;
0000b0 0b89 LSRS r1,r1,#14
;;;1028 presc = ADCPrescTable[tmp];
0000b2 4d07 LDR r5,|L13.208|
0000b4 5c6b LDRB r3,[r5,r1]
;;;1029 /* ADCCLK clock frequency */
;;;1030 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0000b6 68c5 LDR r5,[r0,#0xc]
0000b8 fbb5f5f3 UDIV r5,r5,r3
0000bc 6105 STR r5,[r0,#0x10]
;;;1031 }
0000be bd30 POP {r4,r5,pc}
;;;1032
ENDP
|L13.192|
DCD 0x40021000
|L13.196|
DCD 0x007a1200
|L13.200|
DCD 0x003d0900
|L13.204|
DCD APBAHBPrescTable
|L13.208|
DCD ADCPrescTable
AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2
RCC_GetFlagStatus PROC
;;;1325 */
;;;1326 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000000 b510 PUSH {r4,lr}
;;;1327 {
000002 4601 MOV r1,r0
;;;1328 uint32_t tmp = 0;
000004 2200 MOVS r2,#0
;;;1329 uint32_t statusreg = 0;
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