📄 lib_emac.h
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//*------------------------------------------------------------------------------------------------
//* 文件名 : lib_emac.h
//* 功能描述 : EMAC外设的函数库头文件
//* 作者 : yangzheyu@ict.ac.cn
//* 版本 : 0.1
//* 建立日期、时间 : 2010/10/24
//* 最近修改日期、时间 :
//* 修改原因 :
//*------------------------------------------------------------------------------------------------
#include "OS_CPU.h"
#ifndef __lib_emac_h
#define __lib_emac_h
#define DM9KS_ID 0x90000A46
#define DM9000_NCR 0x00
#define DM9000_NSR 0x01
#define DM9000_TCR 0x02
#define DM9000_TSR1 0x03
#define DM9000_TSR2 0x04
#define DM9000_RCR 0x05
#define DM9000_RSR 0x06
#define DM9000_ROCR 0x07
#define DM9000_BPTR 0x08
#define DM9000_FCTR 0x09
#define DM9000_FCR 0x0A
#define DM9000_EPCR 0x0B
#define DM9000_EPAR 0x0C
#define DM9000_EPDRL 0x0D
#define DM9000_EPDRH 0x0E
#define DM9000_WCR 0x0F
#define DM9000_PAR 0x10
#define DM9000_MAR 0x16
#define DM9000_GPCR 0x1e
#define DM9000_GPR 0x1f
#define DM9000_TRPAL 0x22
#define DM9000_TRPAH 0x23
#define DM9000_RWPAL 0x24
#define DM9000_RWPAH 0x25
#define DM9000_VIDL 0x28
#define DM9000_VIDH 0x29
#define DM9000_PIDL 0x2A
#define DM9000_PIDH 0x2B
#define DM9000_CHIPR 0x2C
#define DM9000_SMCR 0x2F
#define DM9000_MRCMDX 0xF0
#define DM9000_MRCMD 0xF2
#define DM9000_MRRL 0xF4
#define DM9000_MRRH 0xF5
#define DM9000_MWCMDX 0xF6
#define DM9000_MWCMD 0xF8
#define DM9000_MWRL 0xFA
#define DM9000_MWRH 0xFB
#define DM9000_TXPLL 0xFC
#define DM9000_TXPLH 0xFD
#define DM9000_ISR 0xFE
#define DM9000_IMR 0xFF
// NCR (Network Control Register)
#define NCR_EXT_PHY (1 << 7) // 1 ==> external PHY, 0 ==> internal
#define NCR_WAKEEN (1 << 6) // enable wakeup events
#define NCR_FCOL (1 << 4) // force collision mode (test)
#define NCR_FDX (1 << 3) // full duplex (read-only for internal phy)
#define NCR_LBK_NOR (0 << 1) // loopback off
#define NCR_LBK_MAC (1 << 1) // MAC loopback
#define NCR_LBK_PHY (2 << 1) // PHY loopback
#define NCR_RST (1 << 0) // Reset (auto-clears after 10us)
// NSR (Network Status Register)
#define NSR_SPEED (1 << 7) // 0 = 100Mbps, 1 = 10Mbps
#define NSR_LINKST (1 << 6) // link status (1 = okay)
#define NSR_WAKEST (1 << 5) // wake status (clear by read)
#define NSR_TX2END (1 << 3) // TX packet 2 complete
#define NSR_TX1END (1 << 2) // TX packet 1 complete
#define NSR_RXOV (1 << 1) // RX overflow
// TCR (TX Control Register)
#define TCR_TJDIS (1 << 6) // TX jabber disable
#define TCR_EXCECM (1 << 5) // 0 = abort after 15 collisions
#define TCR_PAD_DIS2 (1 << 4)
#define TCR_CRC_DIS2 (1 << 3)
#define TCR_PAD_DIS1 (1 << 2)
#define TCR_CRC_DIS1 (1 << 1)
#define TCR_TXREQ (1 << 0)
// TSR (TX Status Register)
#define TSR_TJTO (1 << 7)
#define TSR_LC (1 << 6)
#define TSR_NC (1 << 5)
#define TSR_LCOL (1 << 4)
#define TSR_COL (1 << 3)
#define TSR_EC (1 << 2)
// RCR (RX Control Register)
#define RCR_WTDIS (1 << 6)
#define RCR_DIS_LONG (1 << 5)
#define RCR_DIS_CRC (1 << 4)
#define RCR_ALL (1 << 3)
#define RCR_RUNT (1 << 2)
#define RCR_PRMSC (1 << 1)
#define RCR_RXEN (1 << 0)
// RSR (RX Status Register)
#define RSR_RF (1 << 7)
#define RSR_MF (1 << 6)
#define RSR_LCS (1 << 5)
#define RSR_RWTO (1 << 4)
#define RSR_PLE (1 << 3)
#define RSR_AE (1 << 2)
#define RSR_CE (1 << 1)
#define RSR_FOE (1 << 0)
// FCR (Flow Control Register)
#define FCR_TXPO (1 << 7)
#define FCR_TXPF (1 << 6)
#define FCR_TXPEN (1 << 5)
#define FCR_BKPA (1 << 4)
#define FCR_BKPM (1 << 3)
#define FCR_RXPS (1 << 2)
#define FCR_RXPCS (1 << 1)
#define FCR_FLCE (1 << 0)
// EPCR (EEPROM & PHY Control Register)
#define EPCR_REEP (1 << 5)
#define EPCR_WEP (1 << 4)
#define EPCR_EPOS (1 << 3)
#define EPCR_ERPRR (1 << 2)
#define EPCR_ERPRW (1 << 1)
#define EPCR_ERRE (1 << 0)
// WCR (Wakeup Control Register)
#define WCR_LINKEN (1 << 5)
#define WCR_SAMPLEEN (1 << 4)
#define WCR_MAGICEN (1 << 3)
#define WCR_LINKST (1 << 2)
#define WCR_SAMPLEST (1 << 1)
#define WCR_MAGIGST (1 << 0)
// SMCR (Special Mode Control Register)
#define SMCR_SM_EN (1 << 7)
#define SMCR_FLC (1 << 2)
#define SMCR_FB1 (1 << 1)
#define SMCR_FB0 (1 << 0)
// ISR (Interrupt Status Register)
#define ISR_IOMODE_16 (0 << 6)
#define ISR_IOMODE_32 (1 << 6)
#define ISR_IOMODE_8 (2 << 6)
#define ISR_ROOS (1 << 3)
#define ISR_ROS (1 << 2)
#define ISR_PTS (1 << 1)
#define ISR_PRS (1 << 0)
// IMR (Interrupt Mask Register)
#define IMR_PAR (1 << 7)
#define IMR_ROOM (1 << 3)
#define IMR_ROM (1 << 2)
#define IMR_PTM (1 << 1)
#define IMR_PRM (1 << 0)
#define NB_TX_BUFS 32 //* 发送缓冲区个数
#define ETH_TX_BUF_SIZE 256 //* 发送缓冲区大小
#define NB_RX_BUFS 32 //* 接收缓冲区个数
#define ETH_RX_BUF_SIZE 128 //* EMAC数据手册规定接收缓冲区仅占128字节大小，128 * 32接收缓冲区共4096字节
#define MACPACKETS_STK_LENGH 1024
#define DM9KS_VID_L 0x28
#define DM9KS_VID_H 0x29
#define DM9KS_PID_L 0x2A
#define DM9KS_PID_H 0x2B
/* 用的是总线的方式访问的网卡里面的寄存器 */
#define DM9KS_BASE_ADDR_ETH0 0x18000000//nGCS5
#define DM9KS_Index (*((volatile unsigned short *)(DM9KS_BASE_ADDR_ETH0 + 0x300)))
#define DM9KS_Data (*((volatile unsigned short *)(DM9KS_BASE_ADDR_ETH0 + 0x304)))
/* DM9000提供给外面的接口只有两个，一个地址寄存器和一个命令寄存器，其他的都是通过这两个操作的 */
#define DM_ADD (*((volatile unsigned short *) 0x18000300))
#define DM_CMD (*((volatile unsigned short *) 0x18000304))
#define RWIDE 50
#define buffer_size 1500
typedef struct buffer_pool{
struct buffer_pool * next;
INT16S leng;
char data[buffer_size];
};
struct buffer_pool * GetInputPacketLen( void);
void EMACInit(void);
void EMACReadPacket(struct buffer_pool * temp,char *pbTo, INT16S uwSegmentLen, BOOLEAN blIsLastPbuf);
BOOLEAN EMACSendPacket(char *pbFrom, INT32U ulLength, BOOLEAN blIsEndOfFrame);
#define Printf Uart_Printf
#endif⌨️ 快捷键说明
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