wdbdbgarchlib.c

VxWorks BSP框架源代码包含头文件和驱动

    if ((pDbgRegs->lctrl2 & _PPC_LCTRL2_LW0EN) == _PPC_LCTRL2_LW0EN)
        {
	addr = pDbgRegs->cmpe;
	type = _PPC_LCTRL1_TYPE_E(pDbgRegs->lctrl1) | BRK_HARDWARE;
	}

    else if ((pDbgRegs->lctrl2 & _PPC_LCTRL2_LW1EN) == _PPC_LCTRL2_LW1EN)
        {
	addr = pDbgRegs->cmpf;
	type = _PPC_LCTRL1_TYPE_F(pDbgRegs->lctrl1) | BRK_HARDWARE;
	}

#endif	/* (CPU == PPC5xx) || (CPU == PPC860) */

#if	(CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604)
    if ((pDbgRegs->iabr & _PPC_IABR_BE) == _PPC_IABR_BE)
        {
	addr = _PPC_IABR_ADD(pDbgRegs->iabr);
	type = BRK_INST | BRK_HARDWARE;
	}
#endif	/* (CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604) */

#if	(CPU == PPC604)
    switch (pDbgRegs->dabr & _PPC_DABR_D_MSK)
        {
        case _PPC_DABR_DR:
	    addr = pDbgRegs->dar & ~0x03;	/* 32-bit aligned address */
	    type = BRK_READ | BRK_HARDWARE;
	    break;
	case _PPC_DABR_DW:
	    addr = pDbgRegs->dar & ~0x03;
	    type = BRK_WRITE | BRK_HARDWARE;
	    break;
	case (_PPC_DABR_DR | _PPC_DABR_DW):
	    addr = pDbgRegs->dar & ~0x03;
	    type = BRK_RW | BRK_HARDWARE;
	    break;
	}
#endif	/* (CPU == PPC604) */

#if	(CPU == PPC403)
    switch (pDbgRegs->dbsr & _DBSR_HWBP_MSK)
        {
	case _DBSR_IA1:
	    addr = pDbgRegs->iac1;
	    type = BRK_INST | BRK_HARDWARE;
	    break;
	case _DBSR_IA2:
	    addr = pDbgRegs->iac2;
	    type = BRK_INST | BRK_HARDWARE;
	    break;
	case _DBSR_DR1:
	case _DBSR_DW1:
	    addr = pDbgRegs->dac1;
	    type = _DBCR_D1_ACCESS(pDbgRegs->dbcr) |
	           _DBCR_D1_SIZE(pDbgRegs->dbcr) |
		   BRK_HARDWARE;
	    break;
	case _DBSR_DR2:
	case _DBSR_DW2:
	    addr = pDbgRegs->dac2;
	    type = _DBCR_D2_ACCESS(pDbgRegs->dbcr) |
	           _DBCR_D2_SIZE(pDbgRegs->dbcr) |
		   BRK_HARDWARE;
	    break;
	}

#elif ((CPU == PPC405) || (CPU == PPC405F))
    switch (pDbgRegs->dbsr & _DBSR_HWBP_MSK)
        {
        case _DBSR_IA1:
            addr = pDbgRegs->iac1;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_IA2:
            addr = pDbgRegs->iac2;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_IA3:
            addr = pDbgRegs->iac3;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_IA4:
            addr = pDbgRegs->iac4;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_DR1:
        case _DBSR_DW1:
            addr = pDbgRegs->dac1;
	    dbcr1 = pDbgRegs->dbcr1 & (_DBCR1_D1R | _DBCR1_D2R | \
				       _DBCR1_D1W | _DBCR1_D2W | \
				       _DBCR1_D1S | _DBCR1_D2S);
	    for ( i = 0 ;
		  i < (sizeof(wdbDbgDbcr1ValTable) / (2 * sizeof(UINT32))) ;
		  i++ )
		{
		if (wdbDbgDbcr1ValTable[i][0] == dbcr1)
		    break;
		}
	    type = i | BRK_HARDWARE;
            break;
        case _DBSR_DR2:
        case _DBSR_DW2:
            addr = pDbgRegs->dac2;
	    dbcr1 = pDbgRegs->dbcr1 & (_DBCR1_D1R | _DBCR1_D2R | \
				       _DBCR1_D1W | _DBCR1_D2W | \
				       _DBCR1_D1S | _DBCR1_D2S);
	    for ( i = 0 ;
		  i < (sizeof(wdbDbgDbcr1ValTable) / (2 * sizeof(UINT32))) ;
		  i++ )
		{
		if (wdbDbgDbcr1ValTable[i][1] == dbcr1)
		    break;
		}
	    type = i | BRK_HARDWARE;
            break;
        }
#elif ((CPU == PPC440) || (CPU == PPC85XX))
    switch (pDbgRegs->dbsr & _DBSR_HWBP_MSK)
        {
        case _DBSR_IAC1:
            addr = pDbgRegs->iac1;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_IAC2:
            addr = pDbgRegs->iac2;
            type = BRK_INST | BRK_HARDWARE;
            break;
#if   (CPU != PPC85XX)
        case _DBSR_IAC3:
            addr = pDbgRegs->iac3;
            type = BRK_INST | BRK_HARDWARE;
            break;
        case _DBSR_IAC4:
            addr = pDbgRegs->iac4;
            type = BRK_INST | BRK_HARDWARE;
            break;
#endif  /* CPU != PPC85XX */
        case _DBSR_DAC1R:
        case _DBSR_DAC1W:
            addr = pDbgRegs->dac1;
	    dbcr0 = pDbgRegs->dbcr0 & (_DBCR0_DAC1R | _DBCR0_DAC2R | \
				       _DBCR0_DAC1W | _DBCR0_DAC2W );
	    for ( i = 0 ;
		  i < (sizeof(wdbDbgDbcr0ValTable) / (2 * sizeof(UINT32))) ;
		  i++ )
		{
		if (wdbDbgDbcr0ValTable[i][0] == dbcr0)
		    break;
		}
	    type = i | BRK_HARDWARE;
            break;
        case _DBSR_DAC2R:
        case _DBSR_DAC2W:
            addr = pDbgRegs->dac2;
	    dbcr0 = pDbgRegs->dbcr0 & (_DBCR0_DAC1R | _DBCR0_DAC2R | \
				       _DBCR0_DAC1W | _DBCR0_DAC2W );
	    for ( i = 0 ;
		  i < (sizeof(wdbDbgDbcr0ValTable) / (2 * sizeof(UINT32))) ;
		  i++ )
		{
		if (wdbDbgDbcr0ValTable[i][1] == dbcr0)
		    break;
		}
	    type = i | BRK_HARDWARE;
            break;
        }
#endif	/* (CPU == PPC4xx) */
	    
    if ((addr == 0) && (type == 0))
        return (ERROR);

    *pType = type;
    *pAddr = addr;

    return (OK);
    }

/*******************************************************************************
*
* wdbDbgHwBpHandle - interrupt level handling of hardware breakpoints
*
* This handler gets the debug registers and calls the common handler for
* breakpoints.
*
* NOMANUAL
*/

void wdbDbgHwBpHandle
    (
    void *	pInfo,		/* pointer on info */
    REG_SET *	pRegisters	/* pointer to register set */
    )
    {
    DBG_REGS	dbgRegSet;	/* debug registers */

    wdbDbgRegsGet (&dbgRegSet);
    wdbDbgRegsClear ();
#if	DBG_NO_SINGLE_STEP
    wdbDbgTrap ((INSTR *) pRegisters->pc, pRegisters, pInfo, &dbgRegSet, TRUE);
#else	/* DBG_NO_SINGLE_STEP */
    wdbDbgBreakpoint (pInfo, pRegisters, &dbgRegSet, TRUE);
#endif	/* DBG_NO_SINGLE_STEP */
    }

/*******************************************************************************
*
* wdbDbgRegsGet - get hardware breakpoint registers
*
* This routine reads hardware breakpoint registers.
*/

LOCAL void wdbDbgRegsGet
    (
    DBG_REGS *	pDbgReg		/* debug register set */
    )
    {

#if 	((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860))

    pDbgReg->cmpa = dbgCmpaGet ();		/* get comparator A register */
    pDbgReg->cmpb = dbgCmpbGet ();		/* get comparator B register */
    pDbgReg->cmpc = dbgCmpcGet ();		/* get comparator C register */
    pDbgReg->cmpd = dbgCmpdGet (); 	        /* get comparator D register */
    pDbgReg->cmpe = dbgCmpeGet ();	     	/* get comparator E register */
    pDbgReg->cmpf = dbgCmpfGet ();	     	/* get comparator F register */
    pDbgReg->lctrl1 = dbgLctrl1Get ();     	/* get LCTRL1 register */
    pDbgReg->lctrl2 = dbgLctrl2Get ();     	/* get LCTRL2 register */
    pDbgReg->ictrl = dbgIctrlGet ();     	/* get ICTRL register */

#elif	(CPU == PPC603) || (CPU ==PPCEC603) || (CPU == PPC604)

    pDbgReg->iabr = wdbDbgIabrGet ();		/* get IABR register */
# if	(CPU == PPC604)
    pDbgReg->dabr = wdbDbgDabrGet ();		/* get DABR register */
    pDbgReg->dar = wdbDbgDarGet ();		/* get DAR register */
# endif	/* (CPU == PPC604) */

#elif	 (CPU == PPC403) 

    pDbgReg->dbcr = wdbDbgDbcrGet ();		/* get DBCR register */
    pDbgReg->dbsr = wdbDbgDbsrGet ();		/* get DBSR register */
    pDbgReg->dac1 = wdbDbgDac1Get ();		/* get DAC1 register */
    pDbgReg->dac2 = wdbDbgDac2Get ();		/* get DAC2 register */
    pDbgReg->iac1 = wdbDbgIac1Get ();		/* get IAC1 register */
    pDbgReg->iac2 = wdbDbgIac2Get ();		/* get IAC2 register */
    pDbgReg->msr = vxMsrGet ();			/* get MSR register */

#elif    ((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
	  (CPU == PPC85XX))

    pDbgReg->dbcr0= wdbDbgDbcr0Get ();           /* get DBCR0 register */
    pDbgReg->dbcr1= wdbDbgDbcr1Get ();           /* get DBCR1 register */
# if	((CPU == PPC440) || (CPU == PPC85XX))
    pDbgReg->dbcr2= wdbDbgDbcr2Get ();           /* get DBCR2 register */
# endif	/* CPU == PPC440, PPC85XX */
    pDbgReg->dbsr = wdbDbgDbsrGet ();           /* get DBSR register */
    pDbgReg->dac1 = wdbDbgDac1Get ();           /* get DAC1 register */
    pDbgReg->dac2 = wdbDbgDac2Get ();           /* get DAC2 register */
    pDbgReg->iac1 = wdbDbgIac1Get ();           /* get IAC1 register */
    pDbgReg->iac2 = wdbDbgIac2Get ();           /* get IAC2 register */
#if   (CPU != PPC85XX)
    pDbgReg->iac3 = wdbDbgIac3Get ();           /* get IAC3 register */
    pDbgReg->iac4 = wdbDbgIac4Get ();           /* get IAC4 register */
#endif  /* CPU != PPC85XX */
    pDbgReg->msr = vxMsrGet ();                 /* get MSR register */

#endif	/* PPC5xx | PPC860 : PPC60x : PPC403 : PPC405x */
    }

/*******************************************************************************
*
* wdbDbgRegsSet - set hardware breakpoint registers
*
* This routine sets hardware breakpoint registers.
*
* NOMANUAL
*/

void wdbDbgRegsSet
    (
    DBG_REGS *	pDbgReg		/* debug register set */
    )
    {

#if 	((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860))

    dbgCmpaSet (pDbgReg->cmpa);			/* set comparator A register */
    dbgCmpbSet (pDbgReg->cmpb);			/* set comparator B register */
    dbgCmpcSet (pDbgReg->cmpc);			/* set comparator C register */
    dbgCmpdSet (pDbgReg->cmpd);			/* set comparator D register */
    dbgCmpeSet (pDbgReg->cmpe);			/* set comparator E register */
    dbgCmpfSet (pDbgReg->cmpf);			/* set comparator F register */
    dbgLctrl1Set (pDbgReg->lctrl1);		/* set LCTRL1 register */
    dbgLctrl2Set (pDbgReg->lctrl2);		/* set LCTRL2 register */

    /* change only used bits of ICTRL register */

    dbgIctrlSet (pDbgReg->ictrl | dbgIctrlGet ());	/* set ICTRL register */

#elif	(CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604)

    wdbDbgIabrSet (pDbgReg->iabr);		/* set IABR regsiter */
# if	(CPU == PPC604)
    wdbDbgDabrSet (pDbgReg->dabr);		/* set DABR register */
# endif	/* (CPU == PPC604) */

#elif	(CPU == PPC403)

    wdbDbgDbcrSet (pDbgReg->dbcr);		/* set DBCR register */
    wdbDbgDac1Set (pDbgReg->dac1);		/* set DAC1 register */
    wdbDbgDac2Set (pDbgReg->dac2);		/* set DAC2 register */
    wdbDbgIac1Set (pDbgReg->iac1);		/* set IAC1 register */
    wdbDbgIac2Set (pDbgReg->iac2);		/* set IAC2 register */
    vxMsrSet (pDbgReg->msr | vxMsrGet ());	/* set MSR register */

#elif   ((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
	 (CPU == PPC85XX))

    wdbDbgDbcr0Set (pDbgReg->dbcr0);            /* set DBCR0 register */
    wdbDbgDbcr1Set (pDbgReg->dbcr1);            /* set DBCR1 register */
# if	((CPU == PPC440) || (CPU == PPC85XX))
    wdbDbgDbcr2Set (pDbgReg->dbcr2);            /* set DBCR2 register */
# endif	/* CPU == PPC440, PPC85XX */
    wdbDbgDac1Set (pDbgReg->dac1);              /* set DAC1 register */
    wdbDbgDac2Set (pDbgReg->dac2);              /* set DAC2 register */
    wdbDbgIac1Set (pDbgReg->iac1);              /* set IAC1 register */
    wdbDbgIac2Set (pDbgReg->iac2);              /* set IAC2 register */
#if   (CPU != PPC85XX)
    wdbDbgIac3Set (pDbgReg->iac3);              /* set IAC3 register */
    wdbDbgIac4Set (pDbgReg->iac4);              /* set IAC4 register */
#endif  /* CPU != PPC85XX */
    vxMsrSet (pDbgReg->msr | vxMsrGet ());      /* set MSR register */

#endif	/* PPC5xx | PPC860 : PPC60x : PPC403 : PPC405x */
    }

/*******************************************************************************
*
* wdbDbgRegsClear - clear hardware breakpoint registers
*
* This routine clears hardware breakpoint registers.
*
* NOMANUAL
*/

void wdbDbgRegsClear (void)
    {

#ifdef	_PPC_MSR_DE
    /* clear debug enable bit in MSR before clobbering DBCRx */
    vxMsrSet (vxMsrGet () & ~_PPC_MSR_DE);
#endif	/* _PPC_MSR_DE */

#if 	((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860))

    dbgCmpaSet (0);			/* clear comparator A register */
    dbgCmpbSet (0);			/* clear comparator B register */
    dbgCmpcSet (0);			/* clear comparator C register */
    dbgCmpdSet (0);			/* clear comparator D register */
    dbgCmpeSet (0);			/* clear comparator E register */
    dbgCmpfSet (0);			/* clear comparator F register */
    dbgLctrl1Set (0);			/* clear LCTRL1 register */
    dbgLctrl2Set (0);			/* clear LCTRL2 register */

    /* clear only used bits of ICTRL register */

    dbgIctrlSet (dbgIctrlGet () & ~_PPC_ICTRL_HWBP_MSK);

#elif	(CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604)

    wdbDbgIabrSet (0);			/* clear IABR register */
# if	(CPU == PPC604)
    wdbDbgDabrSet (0);			/* clear DABR register */

    /* clear only the breakpoint bit of the DSISR */

    vxDsisrSet (vxDsisrGet () & ~_PPC_DSISR_BRK);
# endif	/* (CPU == PPC604) */

#elif	(CPU == PPC403)

    wdbDbgDbcrSet (0);				/* clear DBCR register */
    wdbDbgDac1Set (0);				/* clear DAC1 register */
    wdbDbgDac2Set (0);				/* clear DAC2 register */
    wdbDbgIac1Set (0);				/* clear IAC1 register */
    wdbDbgIac2Set (0);				/* clear IAC2 register */
    wdbDbgDbsrSet (_DBSR_HWBP_MSK);		/* clear DBSR register */

#elif   ((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
	 (CPU == PPC85xx))

    wdbDbgDbcr0Set (0);                         /* clear DBCR0 register */
    wdbDbgDbcr1Set (0);                         /* clear DBCR1 register */
# if	((CPU == PPC440) || (CPU == PPC85XX))
    wdbDbgDbcr2Set (0);                         /* clear DBCR2 register */
# endif	/* CPU == PPC440 || CPU == PPC85XX */
    wdbDbgDac1Set (0);                          /* clear DAC1 register */
    wdbDbgDac2Set (0);                          /* clear DAC2 register */
    wdbDbgIac1Set (0);                          /* clear IAC1 register */
    wdbDbgIac2Set (0);                          /* clear IAC2 register */
#if   (CPU != PPC85XX)
    wdbDbgIac3Set (0);                          /* clear IAC3 register */
    wdbDbgIac4Set (0);                          /* clear IAC4 register */
#endif  /* CPU != PPC85XX */
    wdbDbgDbsrSet (_DBSR_HWBP_MSK);             /* clear DBSR register */

#endif	/* PPC5xx | PPC860 : PPC60x : PPC403 : PPC405x | PPC440 : PPC85XX */
    }

#endif	/* DBG_HARDWARE_BP */