📄 wdbdbgarchlib.c
字号:
break; case BRK_INST: case BRK_DATAR4: case BRK_DATAW4: case BRK_DATARW4: if ((addr & 0x03) || (memProbeRtn ((char *) addr, O_RDONLY, 4, (char *) &val) != OK)) return (ERROR); break;# if (CPU == PPC403) case BRK_DATAR16: case BRK_DATAW16: case BRK_DATARW16: if ((addr & 0x0F) || (memProbeRtn ((char *) addr + 0, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 4, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 8, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 12, O_RDONLY, 4, (char *) &val) != OK) ) return (ERROR); break;# elif ((CPU == PPC405) || (CPU == PPC405F)) case BRK_DATAR32: case BRK_DATAW32: case BRK_DATARW32: if ( (memProbeRtn ((char *) addr + 0, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 4, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 8, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 12, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 16, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 20, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 24, O_RDONLY, 4, (char *) &val) != OK) || (memProbeRtn ((char *) addr + 28, O_RDONLY, 4, (char *) &val) != OK) ) return (ERROR); break;# endif /* 40x */#elif ((CPU == PPC440) || (CPU == PPC85XX)) case BRK_DATAR: case BRK_DATAW: case BRK_DATARW: if (memProbeRtn ((char *) addr, O_RDONLY, 1, (char *) &val) != OK) return (ERROR); break; case BRK_INST: if ((addr & 0x03) || (memProbeRtn ((char *) addr, O_RDONLY, 4, (char *) &val) != OK)) return (ERROR); break;#endif /* PPC5xx | PPC60x | PPC860 : PPC40x */ default: break; } return (OK); }/********************************************************************************* wdbDbgHwBpSet - set the Development Support Registers** Access is the type of access that will generate a breakpoint (depends on the* architecture).** NOMANUAL*/STATUS wdbDbgHwBpSet ( DBG_REGS * pDbgRegs, /* debug registers */ UINT32 access, /* access type */ UINT32 addr /* breakpoint addr */ ) { int status = OK; switch (access) { case BRK_INST:#if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860)) /* take the first free instruction breakpoint register and set it */ if ((pDbgRegs->ictrl & _PPC_ICTRL_SIW0EN) != _PPC_ICTRL_SIW0EN) { pDbgRegs->cmpa = addr; pDbgRegs->ictrl |= _PPC_ICTRL_CTA(_PPC_ICTRL_CT_EQ) | _PPC_ICTRL_IW0_A | _PPC_ICTRL_SIW0EN; } else if ((pDbgRegs->ictrl & _PPC_ICTRL_SIW1EN) != _PPC_ICTRL_SIW1EN) { pDbgRegs->cmpb = addr; pDbgRegs->ictrl |= _PPC_ICTRL_CTB(_PPC_ICTRL_CT_EQ) | _PPC_ICTRL_IW1_B | _PPC_ICTRL_SIW1EN; } else if ((pDbgRegs->ictrl & _PPC_ICTRL_SIW2EN) != _PPC_ICTRL_SIW2EN) { pDbgRegs->cmpc = addr; pDbgRegs->ictrl |= _PPC_ICTRL_CTC(_PPC_ICTRL_CT_EQ) | _PPC_ICTRL_IW2_C | _PPC_ICTRL_SIW2EN; } else if ((pDbgRegs->ictrl & _PPC_ICTRL_SIW3EN) != _PPC_ICTRL_SIW3EN) { pDbgRegs->cmpd = addr; pDbgRegs->ictrl |= _PPC_ICTRL_CTD(_PPC_ICTRL_CT_EQ) | _PPC_ICTRL_IW3_D | _PPC_ICTRL_SIW3EN; } else#elif (CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604) if ((pDbgRegs->iabr & _PPC_IABR_BE) != _PPC_IABR_BE) { pDbgRegs->iabr = _PPC_IABR_ADD(addr) |# if (CPU == PPC604) (mmuPpcIEnabled ? _PPC_IABR_TE : 0) |# endif /* (CPU == PPC604) */ _PPC_IABR_BE; } else#elif (CPU == PPC403) if ((pDbgRegs->dbcr & _DBCR_IA1) != _DBCR_IA1) { pDbgRegs->iac1 = addr; pDbgRegs->dbcr |= _DBCR_IDM | _DBCR_IA1; } else if ((pDbgRegs->dbcr & _DBCR_IA2) != _DBCR_IA2) { pDbgRegs->iac2 = addr; pDbgRegs->dbcr |= _DBCR_IDM | _DBCR_IA2; } else#elif ((CPU == PPC405) || (CPU == PPC405F)) if ((pDbgRegs->dbcr0 & _DBCR0_IA1) != _DBCR0_IA1) { pDbgRegs->iac1 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IA1; } else if ((pDbgRegs->dbcr0 & _DBCR0_IA2) != _DBCR0_IA2) { pDbgRegs->iac2 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IA2; } else if ((pDbgRegs->dbcr0 & _DBCR0_IA3) != _DBCR0_IA3) { pDbgRegs->iac3 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IA3; } else if ((pDbgRegs->dbcr0 & _DBCR0_IA4) != _DBCR0_IA4) { pDbgRegs->iac4 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IA4; } else#elif ((CPU == PPC440) || (CPU == PPC85XX)) if ((pDbgRegs->dbcr0 & _DBCR0_IAC1) != _DBCR0_IAC1) { pDbgRegs->iac1 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IAC1; } else if ((pDbgRegs->dbcr0 & _DBCR0_IAC2) != _DBCR0_IAC2) { pDbgRegs->iac2 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IAC2; }#if (CPU != PPC85XX) else if ((pDbgRegs->dbcr0 & _DBCR0_IAC3) != _DBCR0_IAC3) { pDbgRegs->iac3 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IAC3; } else if ((pDbgRegs->dbcr0 & _DBCR0_IAC4) != _DBCR0_IAC4) { pDbgRegs->iac4 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM | _DBCR0_IAC4; }#endif /* CPU != PPC85XX */ else#endif /* PPC5xx | PPC860 : PPC60x : PPC403 : PPC405x */ /* no more free breakpoint register */ status = WDB_ERR_HW_REGS_EXHAUSTED; break;#if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860)) case BRK_READ: case BRK_WRITE: case BRK_RW: /* take the first free data breakpoint register and set it */ if ((pDbgRegs->lctrl2 & _PPC_LCTRL2_LW0EN) != _PPC_LCTRL2_LW0EN) { pDbgRegs->cmpe = addr; pDbgRegs->lctrl1 |= _PPC_LCTRL1_CTE(_PPC_LCTRL1_CT_EQ) | _PPC_LCTRL1_CRWE(access); pDbgRegs->lctrl2 |= _PPC_LCTRL2_LW0LA_E | _PPC_LCTRL2_LW0LADC | _PPC_LCTRL2_LW0EN | _PPC_LCTRL2_SLW0EN; } else if ((pDbgRegs->lctrl2 & _PPC_LCTRL2_LW1EN) != _PPC_LCTRL2_LW1EN) { pDbgRegs->cmpf = addr; pDbgRegs->lctrl1 |= _PPC_LCTRL1_CTF(_PPC_LCTRL1_CT_EQ) | _PPC_LCTRL1_CRWF(access); pDbgRegs->lctrl2 |= _PPC_LCTRL2_LW1LA_F | _PPC_LCTRL2_LW1LADC | _PPC_LCTRL2_LW1EN | _PPC_LCTRL2_SLW1EN; } else /* no more free breakpoint register */ status = WDB_ERR_HW_REGS_EXHAUSTED; break;#elif (CPU == PPC604) case BRK_READ: if (!(pDbgRegs->dabr & (_PPC_DABR_DW | _PPC_DABR_DR))) pDbgRegs->dabr = _PPC_DABR_DAB(addr) | (mmuPpcDEnabled ? _PPC_DABR_BT : 0) | _PPC_DABR_DR; else status = WDB_ERR_HW_REGS_EXHAUSTED; break; case BRK_WRITE: if (!(pDbgRegs->dabr & (_PPC_DABR_DW | _PPC_DABR_DR))) pDbgRegs->dabr = _PPC_DABR_DAB(addr) | (mmuPpcDEnabled ? _PPC_DABR_BT : 0) | _PPC_DABR_DW; else status = WDB_ERR_HW_REGS_EXHAUSTED; break; case BRK_RW: if (!(pDbgRegs->dabr & (_PPC_DABR_DW | _PPC_DABR_DR))) pDbgRegs->dabr = _PPC_DABR_DAB(addr) | (mmuPpcDEnabled ? _PPC_DABR_BT : 0) | _PPC_DABR_DR | _PPC_DABR_DW; else status = WDB_ERR_HW_REGS_EXHAUSTED; break;#elif (CPU == PPC403) case BRK_DATAR1: case BRK_DATAW1: case BRK_DATARW1: case BRK_DATAR2: case BRK_DATAW2: case BRK_DATARW2: case BRK_DATAR4: case BRK_DATAW4: case BRK_DATARW4: case BRK_DATAR16: case BRK_DATAW16: case BRK_DATARW16: if (!(pDbgRegs->dbcr & (_DBCR_D1R | _DBCR_D1W))) { pDbgRegs->dac1 = addr; pDbgRegs->dbcr |= _DBCR_IDM | _DBCR_D1A(access) | _DBCR_D1S(access); } else if (!(pDbgRegs->dbcr & (_DBCR_D2R | _DBCR_D2W))) { pDbgRegs->dac2 = addr; pDbgRegs->dbcr |= _DBCR_IDM | _DBCR_D2A(access) | _DBCR_D2S(access); } else status = WDB_ERR_HW_REGS_EXHAUSTED; break;#elif ((CPU == PPC405) || (CPU == PPC405F)) case BRK_DATAR1: case BRK_DATAW1: case BRK_DATARW1: case BRK_DATAR2: case BRK_DATAW2: case BRK_DATARW2: case BRK_DATAR4: case BRK_DATAW4: case BRK_DATARW4: case BRK_DATAR32: case BRK_DATAW32: case BRK_DATARW32: if (!(pDbgRegs->dbcr1 & (_DBCR1_D1R | _DBCR1_D1W))) { pDbgRegs->dac1 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM; pDbgRegs->dbcr1 |= wdbDbgDbcr1ValTable [access][0]; } else if (!(pDbgRegs->dbcr1 & (_DBCR1_D2R | _DBCR1_D2W))) { pDbgRegs->dac2 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM; pDbgRegs->dbcr1 |= wdbDbgDbcr1ValTable [access][1]; } else status = WDB_ERR_HW_REGS_EXHAUSTED; break;#elif ((CPU == PPC440) || (CPU == PPC85XX)) case BRK_DATAR: case BRK_DATAW: case BRK_DATARW: if (!(pDbgRegs->dbcr0 & (_DBCR0_DAC1R | _DBCR0_DAC1W))) { pDbgRegs->dac1 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM; pDbgRegs->dbcr0 |= wdbDbgDbcr0ValTable [access][0]; } else if (!(pDbgRegs->dbcr0 & (_DBCR0_DAC2R | _DBCR0_DAC2W))) { pDbgRegs->dac2 = addr; pDbgRegs->dbcr0 |= _DBCR0_IDM; pDbgRegs->dbcr0 |= wdbDbgDbcr0ValTable [access][1]; } else status = WDB_ERR_HW_REGS_EXHAUSTED; break;#endif /* PPC5xx | PPC860 : PPC604 : PPC403 : PPC405x : PPC440 | PPC85XX */ default: status = WDB_ERR_INVALID_HW_BP; } #if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860)) /* set nonmasked mode, breakpoints are always recognized */ if (status == OK) pDbgRegs->lctrl2 |= _PPC_LCTRL2_BRKNOMSK;#elif (defined(_PPC_MSR_DE)) /* set MSR to enable debug exceptions */ if (status == OK) pDbgRegs->msr |= _PPC_MSR_DE;#endif /* PPC5xx | PPC860 : _PPC_MSR_DE */ return (status) ; }/********************************************************************************* wdbDbgHwBpFind - Find the hardware breakpoint** This routine finds the type and the address of the address of the* hardware breakpoint that is set in the DBG_REGS structure.* Those informations are stored in the breakpoint structure that is passed* in parameter.** RETURNS : OK or ERROR if unable to find the hardware breakpoint** NOMANUAL*/STATUS wdbDbgHwBpFind ( DBG_REGS * pDbgRegs, UINT32 * pType, /* return type info via this pointer */ UINT32 * pAddr /* return address info via this pointer */ ) { int addr = 0; int type = 0;#if ((CPU == PPC405) || (CPU == PPC405F)) UINT32 dbcr1; int i;#endif /* CPU == PPC405x */#if ((CPU == PPC440) || (CPU == PPC85XX)) UINT32 dbcr0; int i;#endif /* CPU == PPC440 || CPU == PPC85XX */#if ((CPU == PPC509) || (CPU == PPC555) || (CPU == PPC860)) switch (pDbgRegs->ictrl & _PPC_ICTRL_SIWEN_MSK) { case _PPC_ICTRL_SIW0EN: addr = pDbgRegs->cmpa; type = BRK_INST | BRK_HARDWARE; break; case _PPC_ICTRL_SIW1EN: addr = pDbgRegs->cmpb; type = BRK_INST | BRK_HARDWARE; break; case _PPC_ICTRL_SIW2EN: addr = pDbgRegs->cmpc; type = BRK_INST | BRK_HARDWARE; break; case _PPC_ICTRL_SIW3EN: addr = pDbgRegs->cmpd; type = BRK_INST | BRK_HARDWARE; break; }
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -