mmuppclib.c

VxWorks BSP框架源代码包含头文件和驱动

    )
    {
    return (mmuPpcPageMap (&mmuGlobalTransTbl, effectiveAddr, physicalAddr));
    }

/******************************************************************************
*
* mmuPpcTranslate - translate a virtual address to a physical address
*
* Traverse the translation table and extract the physical address for the
* given virtual address from the pte corresponding to the virtual address.
*
* RETURNS: OK or ERROR if no pte for given virtual address.
*/

LOCAL STATUS mmuPpcTranslate 
    (
    MMU_TRANS_TBL *	pTransTbl,	/* translation table */
    void *		effectiveAddr,	/* effective address */
    void **		physicalAddr	/* where to place the result */
    )
    {
    PTE *	pPte;		/* PTE address */

    /* 
     * Try to find the PTE corresponding to the <effectiveAddr> in the PTEG
     * table pointed to by the pTransTbl structure,
     * If this PTE can not be found then return ERROR.
     */

    if (mmuPpcPteGet (pTransTbl, effectiveAddr, &pPte) != OK)
	{
	errno = S_mmuLib_NO_DESCRIPTOR;
	return (ERROR);
	}

    /* extact the physical address save in the PTE */

    * physicalAddr = (void *) (((u_int) pPte->bytes.word1 & MMU_PTE_RPN) |
                               ((u_int) effectiveAddr & ~MMU_PTE_RPN));

    return (OK);
    }

/******************************************************************************
*
* mmuPpcCurrentSet - change active translation table
*
*/

 void mmuPpcCurrentSet 
    (
    MMU_TRANS_TBL * pTransTbl	/* new active tranlation table */
    ) 
    {
    int		lockKey;			/* intLock lock key */
    static BOOL	firstTime = TRUE;	/* first time call flag */

    if (firstTime)
	{
	/*
	 * write protect all the pages containing the PTEs allocated for
	 * the global translation table.  Need to do this because when this
	 * memory is allocated, the global translation table doesn't exist yet.
	 */

	 mmuPpcMemPagesWriteDisable (&mmuGlobalTransTbl);
	 mmuPpcMemPagesWriteDisable (pTransTbl);

	 firstTime = FALSE;
	 }

    lockKey = intLock ();

    /* 
     * the SDR1 register MUST NOT be altered when the MMU is enabled
     * (see "PowerPc Mircoprocessor Family: The Programming Environments
     * page 2-40 note Nb 5."
     * If the MMU is enabled then turn it off, change SDR1 and
     * enabled it again. Otherwise change SDR1 value.
     */

    if ((mmuPpcIEnabled)  || (mmuPpcDEnabled))
	{
	mmuPpcEnable (FALSE);			/* disable the MMU */
    	mmuPpcSdr1Set (pTransTbl->hTabOrg | pTransTbl->hTabMask);
	mmuPpcEnable (TRUE);			/* re-enable  the MMu */
	}
    else
	mmuPpcSdr1Set (pTransTbl->hTabOrg | pTransTbl->hTabMask);

    intUnlock (lockKey);
    }

/*******************************************************************************
*
* mmuPpcPteGet - get the address of a PTE of a given effective address
* 
* This routine finds the PTE address corresponding to the <effectiveAddr> in
* the PTEG table pointed to by <pTransTbl> structure. If a matching PTE
* existe, the routine save the PTE address at the address pointed to by <ppPte>.
* If any PTE matching the <effectiveAddr> is not found then the function
* return ERROR.
*
* RETURNS: OK or ERROR.
*/

LOCAL STATUS mmuPpcPteGet
    (
    MMU_TRANS_TBL *	pTransTbl,	/* translation table */
    void *		effectiveAddr,	/* effective address */
    PTE **		ppPte		/* result */
    )
    {
    PTEG *	pPteg1;			/* PTEG 1 address */
    PTEG *	pPteg2;			/* PTEG 2 address */
    UINT	vsid;			/* virtual segment ID */
    UINT	api;			/* abbreviated page index */
    UINT	pteIndex;		/* PTE index in a PTEG */

    /* get the address of both PTEGs, the VSID and API values */

    mmuPpcPtegAddrGet (pTransTbl, effectiveAddr, &pPteg1, &pPteg2, &vsid, &api);

    pteIndex = 0;

    /*
     * read the PTEs of the first group. If one of the PTE matchs
     * the expected PTE then extrats the physical address from the PTE word 1
     * and exits the function with OK. If not, checks the next PTE. If no PTE
     * matchs the expected PTE in the first PTEG then read the second PTEG.
     */

    do
	{
	if ((pPteg1->pte[pteIndex].field.v    == TRUE) &&
	    (pPteg1->pte[pteIndex].field.vsid == vsid) &&
	    (pPteg1->pte[pteIndex].field.api  == api) &&
	    (pPteg1->pte[pteIndex].field.h    == 0 ))
	    {
	    * ppPte = &pPteg1->pte[pteIndex];
	    return (OK);
	    }
	}
    while (++pteIndex < MMU_PTE_BY_PTEG);

    pteIndex = 0;

    /*
     * read the PTEs of the second PTEG. If one of the PTE matchs
     * the expected PTE then extrats the physical address from the PTE word 1
     * and exit the function with OK. If not check the next PTE. If no PTE
     * match the expected PTE then exit the function with ERROR.
     */

    do
	{
	if ((pPteg2->pte[pteIndex].field.v    == TRUE) &&
	    (pPteg2->pte[pteIndex].field.vsid == vsid) &&
	    (pPteg2->pte[pteIndex].field.api  ==  api) &&
	    (pPteg2->pte[pteIndex].field.h    == 1 ))
	    {
	    * ppPte = &pPteg2->pte[pteIndex];
	    return (OK);
	    }
	}
    while (++pteIndex < MMU_PTE_BY_PTEG);

    return (ERROR);
    }
 
/*******************************************************************************
*
* mmuPpcPtegAddrGet - get the address of the two Page Table Entry Groups (PTEG)
*
*/

LOCAL void mmuPpcPtegAddrGet
    (
    MMU_TRANS_TBL *	pTransTbl,		/* translation table */
    void *		effectiveAddr,		/* effective address */
    PTEG **		ppPteg1,		/* page table entry group 1 */
    PTEG **		ppPteg2,		/* page table entry group 2 */
    u_int *		pVirtualSegId,		/* virtual segment Id value */
    u_int *		pAbbrevPageIndex	/* abbreviated page index */
    )
    {
    SR		srVal;			/* segment register value */
    UINT 	pageIndex;		/* page index value */
    UINT	primHash;		/* primary hash value */
    UINT	hashValue1;		/* hash value 1 */
    UINT	hashValue2;		/* hash value 2 */
    UINT	hashValue1L;
    UINT	hashValue1H;
    UINT	hashValue2L;
    UINT	hashValue2H;
    EA		effAddr;

    effAddr = * ((EA *)  &effectiveAddr);

    srVal.value =  mmuPpcSrGet (effAddr.srSelect);

    * pVirtualSegId = srVal.bit.vsid ;

    pageIndex = effAddr.pageIndex;

    * pAbbrevPageIndex = (pageIndex & MMU_EA_API) >> MMU_EA_API_SHIFT;

    primHash = srVal.bit.vsid & MMU_VSID_PRIM_HASH;

    hashValue1 = primHash ^ pageIndex;

    hashValue2 = ~ hashValue1;

    hashValue1L = (hashValue1 & MMU_HASH_VALUE_LOW) << MMU_PTE_HASH_VALUE_LOW_SHIFT;
    hashValue1H = (hashValue1 & MMU_HASH_VALUE_HIGH) >> MMU_HASH_VALUE_HIGH_SHIFT;

    hashValue2L = (hashValue2 & MMU_HASH_VALUE_LOW) << MMU_PTE_HASH_VALUE_LOW_SHIFT;
    hashValue2H = (hashValue2 & MMU_HASH_VALUE_HIGH) >> MMU_HASH_VALUE_HIGH_SHIFT;

    hashValue1H = (hashValue1H & pTransTbl->hTabMask) << MMU_PTE_HASH_VALUE_HIGH_SHIFT ;
    hashValue2H = (hashValue2H & pTransTbl->hTabMask) << MMU_PTE_HASH_VALUE_HIGH_SHIFT;

    * ppPteg1 = (PTEG *) (pTransTbl->hTabOrg | hashValue1H | hashValue1L);

    * ppPteg2 = (PTEG *) (pTransTbl->hTabOrg | hashValue2H | hashValue2L);

    }

/*******************************************************************************
*
* mmuPpcPteUpdate - update a PTE value 
*
*/
LOCAL void  mmuPpcPteUpdate
    (
    PTE *	pteAddr,	/* address of the PTE to update */
    PTE *	pteVal		/* PTE value */
    )
    {

    if ((mmuPpcIEnabled) | (mmuPpcDEnabled))
	{
	mmuPpcEnable (FALSE);			/* disable the mmu */
	memcpy ((void *) pteAddr, pteVal, sizeof (PTE));
	mmuPpcEnable (TRUE);
	}
    else
	memcpy ((void *) pteAddr, pteVal, sizeof (PTE));
    }

#if	(CPU == PPC604)
/*******************************************************************************
*
* mmuPpcBatInitMPC74x5 - Initialize the BAT's on the MPC7455
*
* This routine initializes the I & D BAT's on the MPC7455
*
* RETURNS: None
*/

void mmuPpcBatInitMPC74x5 
  (
  UINT32 *pSysBatDesc /* Pointer to the Bat Descriptor array. */
  )
  {

  /* initialize first 4 w/ pre-existing routine - no status */
  mmuPpcBatInit (pSysBatDesc);

  /* 
   * initialize other 4 w/ MPC 7[45]x specific asm routine,
   *  since it also works for 74[45]x
   *
   *  2*8*4 = 2 (UBAT,LBAT) , 8 (4 IBAT + 4 DBAT) , 4 (sizeof UINT32)
   */
  mmuPpcExtraBatInit ((UINT32 *)((UINT32)pSysBatDesc + 2*8*4));

  /* Turn on extra BAT's in HID0 */
  mmuPpcExtraBatEnableMPC74x5();
  }
    
/*******************************************************************************
*
* mmuPpcBatInitMPC7x5 - Initialize the BAT's on the MPC755
*
* This routine initializes the I & D BAT's on the MPC755
*
* RETURNS: None
*/

void mmuPpcBatInitMPC7x5 
  (
  UINT32 *pSysBatDesc
  )
  {

  /* initialize first 4 w/ pre-existing routine - no status */
  mmuPpcBatInit (pSysBatDesc);

  /* 
   * initialize other 4 w/ MPC 7[45]x specific asm routine
   *
   *  2*8*4 = 2 (UBAT,LBAT) , 8 (4 IBAT + 4 DBAT) , 4 (sizeof UINT32)
   */
  mmuPpcExtraBatInit ((UINT32 *)((UINT32)pSysBatDesc + 2*8*4));


  /* Turn on extra BAT's in HID2 */
  mmuPpcExtraBatEnableMPC7x5();
  }

/******************************************************************************
*
* mmuPpcBatInit750fx - Initialize the BAT's on the IBM PPC750FX
*
* This routine initializes the I & D BAT's on the IBM PPC750FX
*
* RETURNS: None
*/

void mmuPpcBatInit750fx
    (
    UINT32 *pSysBatDesc
    )
    {

    /* initialize first 4 w/ pre-existing routine - no status */
    mmuPpcBatInit (pSysBatDesc);

    /*
     * initialize other 4 w/ PPC 7[45]x specific asm routine,
     *   since it also works for 750FX
     *
     *  2*8*4 = 2 (UBAT,LBAT) , 8 (4 IBAT + 4 DBAT) , 4 (sizeof UINT32)
     */
    mmuPpcExtraBatInit ((UINT32 *)((UINT32)pSysBatDesc + 2*8*4));

    /* No separate enable function:  750FX extra BAT's are always on */
    }
#endif /* CPU == PPC604 */


#if	FALSE			/* under construction */	
/*******************************************************************************
*
* mmuPpcSrRegInit - initialize the Segment Registers (SR)
*
*
*/

STATUS mmuPpcSrRegInit
    (
    PHYS_MEM_DESC *	pPhysMemDesc,	/* phycical Memory description */
    UINT		elementNb,	/* element number in the desc. */
    PTEG *		pPtegTbl,	/* PTEG table */
    MMU_TRANS_TBL *	pTransTbl	/*  */
    )
    {
    SR_TABLE *	pAddrTbl;
    u_int	index;
    void *	address = 0x00;
    u_int	entryNb;
    SR		srVal = 0;
    u_int	hashValue;
    u_int	hashValueL;
    u_int	hashValueH;

    pAddrTbl = (SR_TABLE *) malloc (16 * sizeof (SR_TABLE));

    if (pAddrTbl == NULL)
	return (ERROR);

    /* init the address table */

    for (index = 0; index < 16; index++)
	{
	pAddrTbl[index].lowAddr  = address + 0x01000000 - 1 ;
	pAddrTbl[index].highAddr = address ;
	}

    for (entryNb = 0; entryNb < elementNb; entryNb++)
	{
	index = ((EA)pPhysMemDesc[entryNb]->virtualAddr).srSelect 

	pAddrTbl[index]->lowAddr = min (pAddrTbl[index].lowAddr,
				pPhysMemDesc[entryNb]->virtualAddr);

	index = ((EA) pPhysMemDesc[entryNb]->virtualAddr + len).srSelect 

	pAddrTbl[index]->highAddr = max (pAddrTbl[index].highAddr,
				pPhysMemDesc[entryNb]->virtualAddr + len - 1);

	}

    srVal.bit.t = 0;
    srVal.bit.ks = 1;
    srVal.bit.kp = 1;
    srVal.bit.n = 0;

    hashValueL = (pPtegTbl & MMU_PTE_HASH_VALUE_LOW_MASK) >> MMU_PTE_HASH_VALUE_LOW_SHIFT;

    hashValueH = (pPtegTbl & MMU_PTE_HASH_VALUE_HIGH_MASK) >> MMU_PTE_HASH_VALUE_HIGH_SHIFT;

    hashValueH = (hashValueH & pTransTbl->hTabMask) << MMU_HASH_VALUE_HIGH_SHIFT;

    hashValue = (hashValueH & MMU_HASH_VALUE_HIGH) | (hashValueL & MMU_HASH_VALUE_LOW);
    srVal.bit.vsid = (hashValue ^ pAddrTbl[0]->lowAddr. ;

    for (index = 0; index < 16; index++)
	{


    free (pAddrTbl);

    return (OK);
    }


 void mmmuPpcPteShow 
    (
    MMU_TRANS_TBL *	pTransTbl,		/* translation table */
    void *		effectiveAddr		/* effective address */
    )
    {
    PTE *	pte;

    if (mmuPpcPteGet (pTransTbl, effectiveAddr, &pte) == ERROR)
	return ;

    printf ("v		= %d\n", pte->field.v);
    printf ("vsid	= 0x%x\n", pte->field.vsid);
    printf ("h		= %d\n", pte->field.h);
    printf ("api	= 0x%x\n", pte->field.api);
    printf ("rpn	= 0x%x\n", pte->field.rpn);
    printf ("r		= %d\n", pte->field.r);
    printf ("c		= %d\n", pte->field.c);
    printf ("wimg	= 0x%x\n", pte->field.wimg);
    printf ("pp		= 0x%x\n", pte->field.pp);
    }

#endif