excalib.s

VxWorks BSP框架源代码包含头文件和驱动

/* excALib.s - assembly language exception handling stubs */

/* Copyright 1984-2002 Wind River Systems, Inc. */
	.data
	.globl	copyright_wind_river
	.long	copyright_wind_river

/*
modification history
--------------------
03f,18sep03,mil  Fixed concurrent machine check over critical reg corruption.
03e,13aug03,mil  Added saving of DEAR, ESR, MCSR, MCAR and DBSR.
03d,09jun03,mil  Merged from CP1 to e500.
03c,30jan03,jtp  SPR 78738 exc*Ent needs flush of critical save data before
                 reenabling MMU
03b,13nov02,mil  Updated support for PPC85XX.
03a,03oct02,dtr  Adding save/restore of spefscr spr for 85XX floating point.
02z,03aug02,pcs  Add support for PPC85XX and make it the same as PPC603 for
                 the present.
02y,13jun02,jtp  disable MMU during context restore for 4XX (SPR #78396)
02x,17apr02,jtp  Add PPC440 MMU support
02w,12mar02,mil  Reverted FPSCR sticky status bits clear fix (SPR #24693)
                 for SPR #72980/#73109.
02v,07feb02,mil  Fixed double exception caused by FP unavailability.
                 (SPR #73109/72980)
02u,15jan02,yvp  Fixed PPC604 patch to excEnt (done in 02q for SPR #71240)
02t,19nov01,pch  Rework excVecNum handling for extended vectors.
02s,24oct01,dcb  Clear the sticky bits in the FPCSR when there is a floating
                 point exception.
02q,25oct01,kab  Fix SPR #71240: sync propagates to bus, kills performance
		 cleanup T2.2 macros
02r,05oct01,dtr  Changing _PPC_MSR_EP to _PPC_MSR_IP and also excMsrSet to 
	         use mtmsr not mfmsr. SPR 34977
02q,10sep01,yvp  Fix SPR62760:	Add alignment directive for text section. 
02p,15aug01,pch  Add support for PPC440.  Change test for CPU==PPC4xx
		 to ifdef _PPC_MSR_CE where appropriate.
		 Also reworked SPR 69328 fix to take care of side effects.
02o,27jul01,kab  Fix SPR 69328, excVecNum mask
02n,26jun01,pch  Fix SPR 64511: the DEAR is an SPR, not a DCR
02m,26jun01,kab  Removed ALTIVEC conditional compilation.
02l,14jun01,kab  Fixed Altivec Unavailable exc handler, SPR 68206
02k,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
02j,04dec00,s_m  used bsp functions to read/write BEAR/BESR for 405
02i,30nov00,s_m  fixed bus error handling for 405
02h,25oct00,s_m  renamed PPC405 cpu types
02g,13oct00,sm   removed save/restore of BEAR and BESR for PPC405
02f,13oct00,sm   fixed inclusion of symbol fpfix
02e,31aug00,sm   PPC405 & PPC405F support
02d,26mar99,zl   added PowerPC 509 support, no MSR[IR,DR] bits
02c,13nov98,elg  changed GPR3 restoration register in critical exceptions
02b,18aug98,tpr  added PowerPC EC 603 support.
02a,24dec97,dat  SPR 20104, fixed incorrect use of HIADJ macro
01z,22jul97,tpr  added sync instruction arround HID0 modification (SPR #8976)
01y,18mar97,tam  mask/unmask PPC403 Critical Intr. Enable bit (SPR #8192).
01x,10feb97,tam  restore previous value of MSR[FP] bit in excEnt().
01w,20dec96,tpr  added sync inst. before HID0 modification in excEnt().
01v,24jun96,tpr  added PowerPC 860 support.
01u,19mar96,tpr  fixed the bug with _PPC_MSR_RI bit.
01t,17mar96,tam  cleared BESR with 0.
01s,07mar96,tpr  replaced SPGR1 by SPGR0.
01r,06mar96,tpr  removed SDA.
01q,04mar96,tam  fixed excCrtEnt & excCrtExit for PPC403.
		 added code to save DEAR, BEAR & BESR reg. for PPC403.
01p,01mar96,ms   fixed excExit (typos restoring r4 and r13). Removed excStub.
01o,28feb96,tam  added excCrtExit() for critical exceptions for the PPC403 cpu.
01n,27feb96,ms   removed ".globl excClkStub", fixed sp saving in excEnt.
01m,28jan96,tpr  reworked interrupt and exception handling.
01l,16jan95,tpr  reworked interrupt and exception stub (SPR #5657).
01k,08oct95,tpr  reworked code to include the MMU support.
01j,17jul95,caf  removed dbgBreakpoint reference (PPC403).
01i,16jun95,caf  init r2 and r13 according to EABI standard.
01h,22may95,yao  fixed bug in excEPSet().  moved excTraceStub() to dbgALib.s.
01g,22mar95,caf  put #ifdefs around sdata references, fixed internal comments.
01f,09feb95,yao  added excCrtStub, excCrtEnt, excCrtExit for PPC403.  cleanup.
		 changed to disable interrupt before restore interrupt context.
01e,07feb95,yao  removed excProgStub, excDbgStub, excExit1 for PPC403.
01d,02feb95,yao  added excProgStub for PPC403.  removed unnecessary
		 function declarations.
	   +caf  cleanup.
01c,05dec94,caf  added _GREEN_TOOL support, changed 'bcr' to 'bclr',
		 changed 'mtcr' to 'mtcrf'.
01b,11oct94,yao  fixed bug when demultipex interrupts.
		 changed to check for null pointer before jumping to isr.
01a,09sep94,yao  written.
*/

/*
DESCRIPTION
This module contains the assembly language exception handling stubs
along with the interrupt handling stubs.

There are no user-callable routines in this module.
*/

#define _ASMLANGUAGE

#include "vxWorks.h"
#include "asm.h"
#include "esf.h"
#include "regs.h"
#include "private/taskLibP.h"
#include "arch/ppc/excPpcLib.h"

#define	INT_STACK_SWITCH	/* we switch interrupt stack by default */

#if	(CPU == PPC405F)
/* Certain versions of PPC405F need a fix for Errata # 18 (lfd) instruction 
 * Note: This errata is numbered 18 for the 405GF and numbered 20 for the
 * D8405
 */
#define PPC405F_ERRATA_18		/* define this to include fix */
#endif	/* CPU == PPC405F */

	/* globals */

	FUNC_EXPORT(excEnt)		/* exception stub */
	FUNC_EXPORT(excExit)		/* exception stub */

#ifdef	_PPC_MSR_IP
	FUNC_EXPORT(excEPSet)		/* set MSR[IP] bit */
#endif	/* _PPC_MSR_IP */

#ifdef	_PPC_MSR_CE
	FUNC_EXPORT(excCrtEnt)		/* exception stub for critical intr. */
	FUNC_EXPORT(excCrtExit)		/* exception stub for critical intr. */
#endif	/* _PPC_MSR_CE */

#ifdef  _PPC_MSR_MCE
        FUNC_EXPORT(excMchkEnt)         /* exception stub for mach chk intr. */
        FUNC_EXPORT(excMchkExit)        /* exception stub for mach chk intr. */
#endif  /* _PPC_MSR_MCE */

	/* externals */
#if	(CPU == PPC405F)
	FUNC_IMPORT(fpfix)		/* 405 GF errata #18 fix */
	FUNC_IMPORT(fpCrtfix)		/* PPC405F errata fix for crt.intrp */
#endif	/* CPU == PPC405F */

#if	((CPU == PPC405) || (CPU == PPC405F))
	FUNC_IMPORT(sysDcrPlbbesrClear)
	FUNC_IMPORT(sysDcrPlbbearGet)
	FUNC_IMPORT(sysDcrPlbbesrGet)
#endif	/* (CPU == PPC405) || (CPU == PPC405F) */

	FUNC_IMPORT(excExcHandle)	/* default exception handler */
	FUNC_IMPORT(excIntHandle)	/* default interrupt handler */
	FUNC_IMPORT(reschedule)		/* exception handler */
	FUNC_IMPORT(sysIntHandler)	/* bsp level int handler */

#if	((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F))
	FUNC_IMPORT(vxPitInt)		/* pit interrupt handler */
	FUNC_IMPORT(vxFitInt)		/* fit interrupt handler */
#else	/* CPU == PPC403 || CPU == PPC405 || CPU == PPC405F */
	FUNC_IMPORT(vxDecInt)		/* decrementer interrupt handler */
#endif	/* CPU == PPC403 || CPU == PPC405 || CPU == PPC405F */

	DATA_IMPORT(readyQHead)		/* ready queue head */
	DATA_IMPORT(kernelState)	/* kernel state */
	DATA_IMPORT(taskIdCurrent)	/* current task identifier */
	DATA_IMPORT(intCnt)		/* interrupt counter */
	DATA_IMPORT(errno)		/* error number */
	DATA_IMPORT(excRtnTbl)		/* table of exception routine to call */
	DATA_IMPORT(excExtendedVectors)	/* non-zero => "long" vectors */

	_WRS_TEXT_SEG_START
	
/******************************************************************************
*
* excEnt - default context saving routine upon exception entrance
*
* NOTE: The stack pointer is already set to the exception stack frame pointer.
*       The exception vector on the stack is saved as  vector offset + 
*       _EXC_CODE_SIZE.
*
* NOMANUAL

* void excEnt()

*/

FUNC_BEGIN(excEnt)
	/* At the entry of this function, the following is done */
	/* mtspr	SPRG3, p0	/@ save P0 to SPRG3 */
	/* mfspr	p0, LR		/@ load LR to P0 */
	/* bla		excEnt		/@ call excEnt */

#if	(CPU == PPC604)
	/*
	 * The PPC604 has HW support for TLB miss, so we can turn on
	 * address xlate now and avoid the cache locking altogether.
	 * Better performance, especially for the 74xx that always
	 * propogates sync insn to bus.
	 */
	mtspr	SPRG0, p1			/* SPRG0 = p1 */
	mtspr	SPRG2, p0			/* SPRG2 = LR */

	mfspr	p0, SRR1			/* p0 = MSRval b4 exception */
	li	p1, _PPC_MSR_IR | _PPC_MSR_DR   /* p1 = mask IR,DR bits */
	and	p0, p0, p1			/* p0 = IR, DR value b4 exc */
						
	mfmsr	p1				/* p1 = MSRval current */
	or	p1, p1, p0			/* p1 = MSRval cur with old */
						/*      IR, DR bits         */
	mtmsr	p1				/* set MSR with old IR, DR */
	isync					/* synchronize */
	mfspr	p0, SPRG2			/* restore LR to p0 */
	mfspr	p1, SPRG0 			/* restore p1 to p1 */
#endif	/* (CPU == PPC604) */

#if	((CPU == PPC603) || (CPU == PPCEC603))
	/* 
	 * When an exception is generated by the processor, it turn off the
	 * MMU. At this moment the cache is not longer controlled by the 
	 * WIMG bits of the MMU. If the DCE bit in the HID0 is set, the cache
	 * is turn on. In this case the register values are written in the cache
	 * and not in the memory. Because VxWorks executes exception handler
	 * with the MMU turned on we don't know if the memory which handles
	 * the register values are cacheable or not. To avoid memory 
	 * coherency problem, the cache lines handling the register values
	 * saved previously should be flush.
	 *
	 * The approach taken here for 603 is to lock the DCACHE controlled by
	 * HID0[DLOCK] and restore HID0 after critical part of ESF is saved.
	 * SPRG0 is used until the restoration is done.
	 *
	 * XXX TPR : ESF should be reworked to reduce the size this cache
	 * flushing.
	 */
	mtspr	SPRG2, p0			/* SPRG2 = LR */

	mfspr	p0, HID0			/* p0 = HID0val */
	mtspr	SPRG0, p0			/* SPRG0 = HID0val */
	ori	p0, p0, _PPC_HID0_DLOCK		/* set the DLOCK bit */
	sync
	mtspr	HID0, p0			/* set HID0 with DLOCK */
	sync

	mfspr	p0, SPRG2			/* restore LR to p0 */
#endif	/* ((CPU == PPC603) || (CPU == PPCEC603)) */

	/*
	 * reserve a room equal to the size of the ESF. This memory space is
	 * taken from the stack of the task which has produce the exception.
	 * This memory space is used to save the processor critical register
	 * values.
	 */

	stwu	sp, - _PPC_ESF_STK_SIZE(sp)	/* allocate ESF */

	stw	p0, _PPC_ESF_LR(sp)		/* save LR */

	mfspr	p0, SPRG3			/* load saved P0 from SPR3 */
	stw	p0, _PPC_ESF_P0(sp)		/* save P0 */

	mfspr	p0, SRR0			/* load saved PC to P0 */
	stw	p0, _PPC_ESF_PC(sp)		/* save PC */

	mfspr	p0, SRR1			/* load saved MSR to P0 */
	stw	p0, _PPC_ESF_MSR(sp)		/* save MSR */

	stw	p1, _PPC_ESF_P1(sp)		/* save general register P1 */

	mfcr	p1				/* load CR to P1 */
	stw	p1, _PPC_ESF_CR(sp)		/* save CR */

#if	(CPU == PPC405F)
	/*
	 * we need the following fix for certain versions of PPC405F
	 */
# ifdef PPC405F_ERRATA_18
	mtspr	SPRG2, p0			/* save P0 (SRR1) */
	mfspr	p1, LR				/* save current LR */
	mtspr	SPRG0, p1
	bl	fpfix				/* handle fix */
	mfspr	p1, SPRG0			/* load LR */
	mtspr	LR, p1
	mfspr	p0, SPRG2			/* restore P0 (SRR1) */
# endif	/* PPC405F_ERRATA_18 */
#endif	/* CPU == PPC405F */


#if	((CPU == PPC603) || (CPU == PPCEC603))
	mfspr	p1, SPRG0			/* p1 = previous saved HID0 */
	sync
	mtspr	HID0, p1			/* restore HID0 w/o DLOCK */
	sync
#endif	/* ((CPU == PPC603) || (CPU == PPCEC603)) */

#if	((CPU == PPC405) || (CPU == PPC405F) || (CPU == PPC440) || \
         (CPU == PPC85XX))
	/*
 	 * Before we reenable the MMU, we need to ensure that the values
	 * we pushed on the stack above are flushed out of cache.
	 */
    	dcbf    0, sp               /* push SP value to memory */

	li  p1, _PPC_ESF_LR
	dcbf    p1, sp              /* push LR value to memory */

	li  p1, _PPC_ESF_P0
	dcbf    p1, sp              /* push P0 value to memory */

	li  p1, _PPC_ESF_PC
	dcbf    p1, sp              /* push PC value to memory */

	li  p1, _PPC_ESF_MSR
	dcbf    p1, sp              /* push MSR value to memory */

	li  p1, _PPC_ESF_P1
	dcbf    p1, sp              /* push P1 value to memory */

	li  p1, _PPC_ESF_CR
	dcbf    p1, sp              /* push CR value to memory */

	sync
#endif	/* CPU == PPC405, PPC405F, PPC440, PPC85XX */

	/* 
	 * Now turn the data or/and instruction MMU on if they were 
	 * previously turned off.
	 * The critical registers are saved. Now the interrupt and machine
	 * check can be re-enabled. If an interrupt or exception is detected
	 * the previous state can be reconstructed.
	 *
	 * Change to the PPC604: MMU has been re-enabled above.
	 * The code below re-enables PPC604 MMU again while re-enabling
	 * interrupts/exceptions, FP -- the MMU is a nop, but cleaner to
	 * leave here, than to make even more complex conditional compile.
	 */

	mfmsr	p1				/* p1 = MSRval current */
						/* p0 should have MSRval app */

/* This is so we can "or" together defined bits, without a tangle of #ifdef */
#ifdef	_PPC_MSR_RI
#define	_MSR_RI	_PPC_MSR_RI
#else  /* _PPC_MSR_RI */
#define	_MSR_RI	0
#endif  /* _PPC_MSR_RI */

#ifdef	_PPC_MSR_FP
#define	_MSR_FP	_PPC_MSR_FP
#else  /* _PPC_MSR_FP */
#define	_MSR_FP	0
#endif  /* _PPC_MSR_FP */

#ifdef	_PPC_MSR_IR
#define	_MSR_IR	_PPC_MSR_IR
#else  /* _PPC_MSR_IR */