vxalib.s

VxWorks BSP框架源代码包含头文件和驱动

*
* RETURNS: content of MCSRR1
*
*/

FUNC_BEGIN(vxMcsrr1Get)
        mfspr   p0, MCSRR1
        blr
FUNC_END(vxMcsrr1Get)

/***************************************************************************
*
* vxMcsrr1Set - this routine sets the content of MCSRR1
*
* RETURNS: none
*
*/

FUNC_BEGIN(vxMcsrr1Set)
        mtspr   MCSRR1, p0
        blr
FUNC_END(vxMcsrr1Set)

/***************************************************************************
*
* vxSpefscrGet - this routine returns the content of SPEFSCR
*
* RETURNS: content of SPEFSCR
*
*/

FUNC_BEGIN(vxSpefscrGet)
        mfspr   p0, SPEFSCR
        blr
FUNC_END(vxSpefscrGet)

/***************************************************************************
*
* vxSpefscrSet - this routine sets the content of SPEFSCR
*
* RETURNS: none
*
*/

FUNC_BEGIN(vxSpefscrSet)
        mtspr   SPEFSCR, p0
        blr
FUNC_END(vxSpefscrSet)

/***************************************************************************
*
* vxDecarSet - this routine sets the content of the DECAR register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxDecarSet)
	mtspr	DECAR,p0			/* set DECAR */
	blr
FUNC_END(vxDecarSet)

/***************************************************************************
*
* vxL1CSR0Get - this routine sets the content of the L1CSR0 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CSR0Get)
	mfspr	p0,L1CSR0			/* get L1CSR0 */
	blr
FUNC_END(vxL1CSR0Get)

/***************************************************************************
*
* vxL1CSR0Set - this routine sets the content of the L1CSR0 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CSR0Set)
	mtspr	L1CSR0,p0			/* set L1CSR0 */
	blr
FUNC_END(vxL1CSR0Set)

/***************************************************************************
*
* vxL1CSR1Get - this routine sets the content of the L1CSR0 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CSR1Get)
	mfspr	p0,L1CSR1			/* get L1CSR1 */
	blr
FUNC_END(vxL1CSR1Get)

/***************************************************************************
*
* vxL1CSR1Set - this routine sets the content of the L1CSR0 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CSR1Set)
	mtspr	L1CSR1,p0			/* set L1CSR1 */
	blr
FUNC_END(vxL1CSR1Set)

/***************************************************************************
*
* vxL1CFG0Get - this routine gets the content of the L1CRG0 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CFG0Get)
	mfspr	p0,L1CFG0			/* get L1CFG0 */
	blr
FUNC_END(vxL1CFG0Get)

/***************************************************************************
*
* vxL1CFG1Get - this routine sets the content of the L1CFG1 register
*
* RETURN: N/A.
*/

FUNC_BEGIN(vxL1CFG1Get)
	mfspr	p0,L1CFG1			/* get L1CSR1 */
	blr
FUNC_END(vxL1CFG1Get)

#elif ((CPU != PPC403) && (CPU != PPC405) && \
       (CPU != PPC440))                         /* CPU==PPC85XX */

/*******************************************************************************
*
* vxDarGet - this routine returns the content of DAR
*
* RETURN: content of dar.
*/
FUNC_BEGIN(vxDarGet)
        mfdar   p0
        blr
FUNC_END(vxDarGet)

/*******************************************************************************
*
* vxDarSet - this routine modifies the content of DAR
*
* RETURN: N/A.
*/
FUNC_BEGIN(vxDarSet)
        mtdar   p0
        blr
FUNC_END(vxDarSet)

/*******************************************************************************
*
* vxDsisrGet - this routine returns the content of DSISR
*
* RETURN: content of dsisr.
*/
FUNC_BEGIN(vxDsisrGet)
        mfdsisr p0
        blr
FUNC_END(vxDsisrGet)

/*******************************************************************************
*
* vxDsisrSet - this routine modifies the content of DSISR
*
* RETURN: N/A.
*/
FUNC_BEGIN(vxDsisrSet)
        mtdsisr p0
        blr
FUNC_END(vxDsisrSet)

#endif  /* CPU == PPC85XX, PPC403, PPC405, PPC440 */

/*******************************************************************************
*
* vxSrr0Get - this routine returns the content of SRR0
*
* RETURN: content of srr0.
*/
FUNC_BEGIN(vxSrr0Get)
        mfsrr0  p0
        blr
FUNC_END(vxSrr0Get)

/*******************************************************************************
*
* vxSrr0Set - this routine modifies the content of SRR0
*
* RETURN: N/A.
*/
FUNC_BEGIN(vxSrr0Set)
        mtsrr0  p0
        blr
FUNC_END(vxSrr0Set)

/*******************************************************************************
*
* vxSrr1Get - this routine returns the content of SRR1
*
* RETURN: content of srr1.
*/
FUNC_BEGIN(vxSrr1Get)
        mfsrr1  p0
        blr
FUNC_END(vxSrr1Get)

/*******************************************************************************
*
* vxSrr1Set - this routine modifies the content of SRR1
*
* RETURN: N/A.
*/
FUNC_BEGIN(vxSrr1Set)
        mtsrr1  p0
        blr
FUNC_END(vxSrr1Set)

/*******************************************************************************
*
* vxFirstBit - this routine returns the first bit set in the register
*
* RETURN: the number of first bit set.
*/
FUNC_BEGIN(vxFirstBit)
	cntlzw	p0, p0				/* first bit set count in p0 */
	blr
FUNC_END(vxFirstBit)

/******************************************************************************
*
* vxPvrGet - Get the processor type from the Processor Version Register
*/

FUNC_BEGIN(vxPvrGet)
	mfspr	p0, PVR
	blr
FUNC_END(vxPvrGet)


	
/******************************************************************************
*
* vxEieio - Execute the eieio instruction to enforce in-order execution
*
* This routine is useful for drivers that try to write I/O registers and
* the registers have an inherent order dependency.
* 
* RETURN: N/A.
*/

FUNC_BEGIN(vxEieio)
	eieio	
	blr
FUNC_END(vxEieio)

/*******************************************************************************
*
* vxPowerDown - turn the processor in reduced power mode
*
* This routine activates the reduced power mode if power management is enabled.
* It is called by the scheduler when the kernel enters the iddle loop.
* The power management mode is selected via the routine vxPowerModeSet().
*
* RETURNS: OK, or ERROR if power management is not supported, or external
* interrupts are disabled.
*
* SEE ALSO: vxPowerModeSet(), vxPowerModeGet().

* STATUS vxPowerDown (void)

*/

FUNC_BEGIN(vxPowerDown)
#if     ((CPU == PPC555) || (CPU == PPC603) || (CPU == PPCEC603) || \
         (CPU == PPC604) || (CPU == PPC860))

	/* test if power management is enabled */

	lis	p0, HIADJ(vxPowMgtEnable)
	lwz	p0, LO(vxPowMgtEnable)(p0)
	cmpwi	p0, TRUE		/* test vxPowMgtEnable == TRUE */
	bne	powerExitOk		/* exit without setting POW bit */
	
	/* test if external interrupt are enabled */

powerEnable:
	mfmsr	p1			/* load p1 with MSR register val */
	rlwinm.	p0, p1, 0, _PPC_MSR_BIT_EE, _PPC_MSR_BIT_EE 
	bne	powerDownGo
	li	p0, -1			/* returns ERROR : external interrupt */
	blr				/* are disabled. */

	/* set MSR(POW) bit */

powerDownGo:
	sync				/* synchronize */
	oris	p1, p1, _PPC_MSR_POW_U	/* set POW bit of MSR */ 
	mtmsr	p1
	isync				/* synchronize */

powerExitOk:
	li	p0, 0			/* returns OK */
	blr

#else	/* CPU==PPC555||CPU==PPC603||CPU==PPCEC603||CPU==PPC604||CPU==PPC860 */

	li      p0, -1                  /* returns ERROR: power management */
	blr				/* is not supported */

#endif	/* CPU==PPC555||CPU==PPC603||CPU==PPCEC603||CPU==PPC604||CPU==PPC860 */
FUNC_END(vxPowerDown)

#if	((CPU == PPC601) || (CPU == PPC603) || (CPU == PPCEC603) || \
	 (CPU == PPC604) || (CPU == PPC85XX))
/*******************************************************************************
*
* vxHid0Set - this routine Set the content of HID0
*/

FUNC_BEGIN(vxHid0Set)
# if	(CPU == PPC604)
	sync
# endif	/* (CPU == PPC604) */
	mtspr	HID0,p0
# if	(CPU == PPC604)
	sync
# endif	/* (CPU == PPC604) */
	blr
FUNC_END(vxHid0Set)

/*******************************************************************************
*
* vxHid0Get - this routine returns the content of HID0
*/

FUNC_BEGIN(vxHid0Get)
	mfspr	p0,HID0
	blr
FUNC_END(vxHid0Get)

/*******************************************************************************
*
* vxHid1Set - this routine Set the content of HID0
*/

FUNC_BEGIN(vxHid1Set)
# if	(CPU == PPC604)
	sync
# endif	/* (CPU == PPC604) */
	mtspr	HID1,p0
# if	(CPU == PPC604)
	sync
# endif	/* (CPU == PPC604) */
	blr
FUNC_END(vxHid1Set)

/*******************************************************************************
*
* vxHid1Get - this routine returns the content of HID1
*/

FUNC_BEGIN(vxHid1Get)
	mfspr	p0,HID1
	blr
FUNC_END(vxHid1Get)

#endif	/* CPU == PPC601, PPC603, PPC604, PPC85XX */

#if	((CPU == PPC509) || (CPU == PPC555)   || (CPU == PPC601) || \
         (CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604) || \
	 (CPU == PPC405F))
/*******************************************************************************
*
* vxFpscrSet - this routine Set the content of FPSCR
*
* RETURN: N/A
*/

FUNC_BEGIN(vxFpscrSet)
	addi	sp, sp, -16		/* reserve some stack */
	stw	p0, 4(sp)		/* push param on the stack */
	li	p0, 0
	stw	p0, 0(sp)		/* clear other half of dword */
	stfd	fr0, 8(sp)		/* push fr0 */
	lfd	fr0, 0(sp)
	mtfsf	255, fr0
	lfd	fr0, 8(sp)		/* pop fr0 */
	addi	sp, sp, +16		/* clean up stack */
	blr
FUNC_END(vxFpscrSet)

/*******************************************************************************
*
* vxFpscrGet - this routine returns the content of FPSCR
*
* RETURN: value of the floating point status and control register (FPSCR).
*/

FUNC_BEGIN(vxFpscrGet)
	addi	sp, sp, -16		/* reserve some stack */
	stfd	fr0, 8(sp)		/* push fr0 */
	mffs	fr0
	stfd	fr0, 0(sp)		/* push FPSCR on the stack */
	lwz	p0, 4(sp)
	lfd	fr0, 8(sp)		/* pop fr0 */
	addi	sp, sp, +16		/* get frame stack */
	blr
FUNC_END(vxFpscrGet)
#endif	/* ((CPU == PPC509) || (CPU == PPC555)   || (CPU == PPC601) || \
            (CPU == PPC603) || (CPU == PPCEC603) || (CPU == PPC604) || \
	    (CPU == PPC405F)) */

/*******************************************************************************
*
* vxTimeBaseSet - set time base
*
* This routine set the time base.  Register p0 has the upper 32 bit value
* and p1 has the lower 32 bit. For CPU==PPC860 the option of locking the key
* registers is there. In this case it is also done in a interrupt handler
* so it needs to interrupt safe. As the routine isn't called that often it's 
* not that wasteful. 
*
* RETURN: N/A.
*/
FUNC_BEGIN(vxTimeBaseSet)
	li      p2, 0
#if 	((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F))
	mtspr	TBLO, p2		/* set TBLO to zero, preventing carry */
	mtspr	TBHI, p0		/* set TBHI */
	mtspr	TBLO, p1		/* set TBLO */
#elif	((CPU == PPC440) || (CPU == PPC85XX))
	mtspr	TBL_W, p2		/* set TBLO to zero, preventing carry */
	mtspr	TBU_W, p0		/* set TBHI */
	mtspr	TBL_W, p1		/* set TBLO */
#else	/* CPU == PPC4xx, PPC85XX */
# if	(CPU == PPC860)
	lis	p5, HIADJ(vx860KeyedRegUsed)
	lwz	p5, LO(vx860KeyedRegUsed)(p5)
	cmpwi	p5, TRUE		/* test  == TRUE */
        bne	vxTimeStateSetStandard  /* branch to normal non keyed reg use */
	mfspr   p4, IMMR		/* move IMMR register to P4 */
	rlwinm  p4, p4, 0, 0, 15	/* the address should be 64K aligned */
        lis     p3, HIADJ(  0x55CCAA33 ) /* KEYED_REG_UNLOCK_VALUE */
        addi    p3, p3, LO( 0x55CCAA33 ) /* KEYED_REG_UNLOCK_VALUE */
	lis     p5, HIADJ(  ~0x55CCAA33 ) /* KEYED_REG_LOCK_VALUE */
        addi    p5, p5, LO( ~0x55CCAA33 ) /* KEYED_REG_LOCK_VALUE */
	mfmsr	p6			/* read msr to p0 */
	INT_MASK(p6,p7)	/* unset ee bit */
	mtmsr	p7			/* disable interrupt */
	sync
        stw     p3, 0x30C(p4) /* unlock TB registers*/
	isync
	mttbl   p2                      /* force TBL to zero */
	mttbu   p0                      /* set TBU */
	mttbl   p1                      /* set TBL */
        stw     p5, 0x30C(p4) /* unlock TB register*/
	mtmsr	p6			/* enable interrupt */
	sync
	blr
vxTimeStateSetStandard:	
# endif	/* CPU == PPC860 */
	mttbl   p2			/* set TBL to zero, preventing carry */
	mttbu   p0			/* set TBU */
	mttbl   p1			/* set TBL */
#endif  /* CPU == PPC4xx, PPC85XX */
	blr
FUNC_END(vxTimeBaseSet)

/*******************************************************************************
*
* vxTimeBaseGet - get time base
*
* RETURN: upper 32 bit value of time in *(uint *)p0, 
*         lower 32 bit value of time in *(uint *)p1.
*/

FUNC_BEGIN(vxTimeBaseGet)

	/* Because of the possibility of a carry from TBL to TBU occurring 
	 * between reads of TBL and TBU, the following reading sequence 
	 * is necessary.
	 */

#if 	((CPU == PPC403) || (CPU == PPC405) || (CPU == PPC405F))
	mfspr	p2, TBHI                /* load from TBHI */
	mfspr	p3, TBLO                /* load from TBLO */
	mfspr	p4, TBHI                /* load from TBHI */
#elif	((CPU == PPC440) || (CPU == PPC85XX))