dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

    {"dcbtst",   _OP(31,  246),     _IFORM_X_22,    0},
    {"dcbz",     _OP(31, 1014),     _IFORM_X_22,    0},
    {"eciwx",    _OP(31,  310),     _IFORM_X_1,     0},
    {"ecowx",    _OP(31,  438),     _IFORM_X_10,    0},
    {"eieio",    _OP(31,  854),     _IFORM_X_23,    0},
    {"eqv",      _OP(31,  284),     _IFORM_X_8,     _IFLAG_RC},
    {"extsb",    _OP(31,  954),     _IFORM_X_11,    _IFLAG_RC},
    {"extsh",    _OP(31,  922),     _IFORM_X_11,    _IFLAG_RC},

#if (defined(HOST) || (CPU == PPC601) || (CPU == PPC603) || (CPU==PPC604) || \
	(CPU == PPC405F))
    {"fabs",     _OP(63,  264),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fctiw",    _OP(63,   14),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fctiwz",   _OP(63,   15),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fcmpo",    _OP(63,   32),     _IFORM_X_17,    _IFLAG_FP_SPEC},
    {"fcmpu",    _OP(63,    0),     _IFORM_X_17,    _IFLAG_FP_SPEC},
    {"fmr",      _OP(63,   72),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fnabs",    _OP(63,  136),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fneg",     _OP(63,   40),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"frsp",     _OP(63,   12),     _IFORM_X_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"lfdux",    _OP(31,  631),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"lfdx",     _OP(31,  599),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"lfsux",    _OP(31,  567),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"lfsx",     _OP(31,  535),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"stfdux",   _OP(31,  759),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"stfdx",    _OP(31,  727),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"stfsux",   _OP(31,  695),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"stfiwx",   _OP(31,  983),     _IFORM_X_24,    _IFLAG_FP_SPEC},
    {"stfsx",    _OP(31,  663),     _IFORM_X_24,    _IFLAG_FP_SPEC},
#endif	/* HOST | 60x | 405F */

    {"icbi",     _OP(31,  982),     _IFORM_X_22,    0},
    {"lbzux",    _OP(31,  119),     _IFORM_X_1,     0},
    {"lbzx",     _OP(31,   87),     _IFORM_X_1,     0},
    {"lhaux",    _OP(31,  375),     _IFORM_X_1,     0},
    {"lhax",     _OP(31,  343),     _IFORM_X_1,     0},
    {"lhbrx",    _OP(31,  790),     _IFORM_X_1,     0},
    {"lhzux",    _OP(31,  311),     _IFORM_X_1,     0},
    {"lhzx",     _OP(31,  279),     _IFORM_X_1,     0},
    {"lswi",     _OP(31,  597),     _IFORM_X_26,    0},
    {"lswx",     _OP(31,  533),     _IFORM_X_1,     0},
    {"lwarx",    _OP(31,   20),     _IFORM_X_1,     0},
    {"lwbrx",    _OP(31,  534),     _IFORM_X_1,     0},
    {"lwzux",    _OP(31,   55),     _IFORM_X_1,     0},
    {"lwzx",     _OP(31,   23),     _IFORM_X_1,     0},
    {"mcrfs",    _OP(63,   64),     _IFORM_X_18,    0},
    {"mcrxr",    _OP(31,  512),     _IFORM_X_19,    0},
    {"mfcr",     _OP(31,   19),     _IFORM_X_5,     0},
    {"mffs",     _OP(63,  583),     _IFORM_X_6,     _IFLAG_RC},
    {"mfmsr",    _OP(31,   83),     _IFORM_X_5,     0},
    {"mfsr",     _OP(31,  595),     _IFORM_X_7,     0},
    {"mfsrin",   _OP(31,  659),     _IFORM_X_3,     0},
    {"mtfsb0",   _OP(63,   70),     _IFORM_X_25,    _IFLAG_RC},
    {"mtfsb1",   _OP(63,   38),     _IFORM_X_25,    _IFLAG_RC},
    {"mtfsfi",   _OP(63,  134),     _IFORM_X_20,    _IFLAG_RC},
    {"mtmsr",    _OP(31,  146),     _IFORM_X_13,    0},
    {"mtsr",     _OP(31,  210),     _IFORM_X_14,    0},
    {"mtsrin",   _OP(31,  242),     _IFORM_X_12,    0},
    {"nand",     _OP(31,  476),     _IFORM_X_8,     _IFLAG_RC},
    {"nor",      _OP(31,  124),     _IFORM_X_8,     _IFLAG_RC},
    {"or",       _OP(31,  444),     _IFORM_X_8,     _IFLAG_RC},
    {"orc",      _OP(31,  412),     _IFORM_X_8,     _IFLAG_RC},
    {"slw",      _OP(31,   24),     _IFORM_X_8,     _IFLAG_RC},
    {"sraw",     _OP(31,  792),     _IFORM_X_8,     _IFLAG_RC},
    {"srawi",    _OP(31,  824),     _IFORM_X_15,    _IFLAG_RC},
    {"srw",      _OP(31,  536),     _IFORM_X_8,     _IFLAG_RC},
    {"stbux",    _OP(31,  247),     _IFORM_X_10,    0},
    {"stbx",     _OP(31,  215),     _IFORM_X_10,    0},
    {"sthbrx",   _OP(31,  918),     _IFORM_X_10,    0},
    {"sthux",    _OP(31,  439),     _IFORM_X_10,    0},
    {"sthx",     _OP(31,  407),     _IFORM_X_10,    0},
    {"stswi",    _OP(31,  725),     _IFORM_X_27,    0},
    {"stswx",    _OP(31,  661),     _IFORM_X_10,    0},
    {"stwbrx",   _OP(31,  662),     _IFORM_X_10,    0},
    {"stwcx.", 1+_OP(31,  150),     _IFORM_X_9,     0},
    {"stwx",     _OP(31,  151),     _IFORM_X_10,    0},
    {"stwux",    _OP(31,  183),     _IFORM_X_10,    0},
    {"sync",     _OP(31,  598),     _IFORM_X_23,    0},

#if	(defined(HOST) || !defined(PPC_NO_REAL_MODE))
    {"tlbia",    _OP(31,  370),     _IFORM_X_23,    0},
#endif	/* HOST || !PPC_NO_REAL_MODE */

    {"tlbie",    _OP(31,  306),     _IFORM_X_2,     0},
    {"tlbsync",  _OP(31,  566),     _IFORM_X_23,    0},
    {"tw",       _OP(31,    4),     _IFORM_X_21,    0},
    {"xor",      _OP(31,  316),     _IFORM_X_8,     _IFLAG_RC},

    {"bcctr",    _OP(19,  528),     _IFORM_XL_1,    _IFLAG_LK},
    {"bclr",     _OP(19,   16),     _IFORM_XL_1,    _IFLAG_LK},
    {"crand",    _OP(19,  257),     _IFORM_XL_2,    0},
    {"crandc",   _OP(19,  129),     _IFORM_XL_2,    0},
    {"creqv",    _OP(19,  289),     _IFORM_XL_2,    0},
    {"crnand",   _OP(19,  225),     _IFORM_XL_2,    0},
    {"crnor",    _OP(19,   33),     _IFORM_XL_2,    0},
    {"cror",     _OP(19,  449),     _IFORM_XL_2,    0},
    {"crorc",    _OP(19,  417),     _IFORM_XL_2,    0},
    {"crxor",    _OP(19,  193),     _IFORM_XL_2,    0},
    {"isync",    _OP(19,  150),     _IFORM_XL_4,    0},
    {"mcrf",     _OP(19,    0),     _IFORM_XL_3,    0},
    {"rfi",      _OP(19,   50),     _IFORM_XL_4,    0},

    {"mfspr",    _OP(31,  339),     _IFORM_XFX_1,   0},
    {"mtspr",    _OP(31,  467),     _IFORM_XFX_4,   0},
    {"mtcrf",    _OP(31,  144),     _IFORM_XFX_2,   0},
    {"mftb",     _OP(31,  371),     _IFORM_XFX_3,   0},

    {"mtfsf",	 _OP(63,  711),     _IFORM_XFL_1,   _IFLAG_RC},

    {"add",      _OP(31,  266),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"addc",     _OP(31,   10),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"adde",     _OP(31,  138),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"addme",    _OP(31,  234),     _IFORM_XO_3,    _IFLAG_RC | _IFLAG_OE},
    {"addze",    _OP(31,  202),     _IFORM_XO_3,    _IFLAG_RC | _IFLAG_OE},
    {"divw",     _OP(31,  491),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"divwu",    _OP(31,  459),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"mulhw",    _OP(31,   75),     _IFORM_XO_2,    _IFLAG_RC},
    {"mulhwu",   _OP(31,   11),     _IFORM_XO_2,    _IFLAG_RC},
    {"mullw",    _OP(31,  235),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"neg",      _OP(31,  104),     _IFORM_XO_3,    _IFLAG_RC | _IFLAG_OE},
    {"subf",     _OP(31,   40),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"subfc",    _OP(31,    8),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"subfe",    _OP(31,  136),     _IFORM_XO_1,    _IFLAG_RC | _IFLAG_OE},
    {"subfme",   _OP(31,  232),     _IFORM_XO_3,    _IFLAG_RC | _IFLAG_OE},
    {"subfze",   _OP(31,  200),     _IFORM_XO_3,    _IFLAG_RC | _IFLAG_OE},

#if (defined(HOST) || (CPU == PPC601) || (CPU == PPC603) || (CPU==PPC604) || \
	(CPU == PPC405F))
    {"fadd",     _OP(63,   21),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fadds",    _OP(59,   21),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fdiv",     _OP(63,   18),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fdivs",    _OP(59,   18),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmadd",    _OP(63,   29),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmadds",   _OP(59,   29),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmsub",    _OP(63,   28),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmsubs",   _OP(59,   28),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmul",     _OP(63,   25),     _IFORM_A_3,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fmuls",    _OP(59,   25),     _IFORM_A_3,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fnmadd",   _OP(63,   31),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fnmadds",  _OP(59,   31),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fnmsub",   _OP(63,   30),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fnmsubs",  _OP(59,   30),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fres",     _OP(59,   24),     _IFORM_A_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"frsqrte",  _OP(63,   26),     _IFORM_A_4,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fsel",     _OP(63,   23),     _IFORM_A_2,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fsub",     _OP(63,   20),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
    {"fsubs",    _OP(59,   20),     _IFORM_A_1,     _IFLAG_RC | _IFLAG_FP_SPEC},
#endif	/* HOST | 60x | 405F */

    /* The following are for the Altivec processor */
#if     (defined(HOST) || ((CPU == PPC604) && (_WRS_ALTIVEC_SUPPORT == TRUE)))

    {"vmaddfp",     _VOP(4,   46),  _IFORM_VA_1B,  _IFLAG_AV_SPEC},
    {"vnmsubfp",    _VOP(4,   47),  _IFORM_VA_1B,  _IFLAG_AV_SPEC},
    {"vmhaddshs",   _VOP(4,   32),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmhraddshs",  _VOP(4,   33),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmladduhm",   _VOP(4,   34),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsumubm",    _VOP(4,   36),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsummbm",    _VOP(4,   37),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsumuhm",    _VOP(4,   38),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsumuhs",    _VOP(4,   39),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsumshm",    _VOP(4,   40),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vmsumshs",    _VOP(4,   41),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vsel",	    _VOP(4,   42),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vperm",       _VOP(4,   43),  _IFORM_VA_1,   _IFLAG_AV_SPEC},
    {"vsldoi",	    _VOP(4,   44),  _IFORM_VA_2,   _IFLAG_AV_SPEC},
    {"vaddubm",	    _VOP(4,    0),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vadduhm",	    _VOP(4,   64),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vadduwm",	    _VOP(4,  128),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vaddcuw",	    _VOP(4,  384),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vaddubs",	    _VOP(4,  512),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vadduhs",	    _VOP(4,  576),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vadduws",	    _VOP(4,  640),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vaddsbs",	    _VOP(4,  768),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vaddshs",	    _VOP(4,  832),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vaddsws",	    _VOP(4,  896),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsububm",	    _VOP(4, 1024),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubuhm",	    _VOP(4, 1088),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubuwm",	    _VOP(4, 1152),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubcuw",	    _VOP(4, 1408),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsububs",	    _VOP(4, 1536),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubuhs",	    _VOP(4, 1600),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubuws",	    _VOP(4, 1664),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubsbs",	    _VOP(4, 1792),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubshs",	    _VOP(4, 1856),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsubsws",	    _VOP(4, 1920),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxub",	    _VOP(4,    2),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxuh",	    _VOP(4,   66),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxuw",	    _VOP(4,  130),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxsb",	    _VOP(4,  258),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxsh",	    _VOP(4,  322),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmaxsw",	    _VOP(4,  386),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminub",	    _VOP(4,  514),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminuh",	    _VOP(4,  578),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminuw",	    _VOP(4,  642),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminsb",	    _VOP(4,  770),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminsh",	    _VOP(4,  834),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vminsw",	    _VOP(4,  898),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavgub",	    _VOP(4, 1026),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavguh",	    _VOP(4, 1090),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavguw",	    _VOP(4, 1154),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavgsb",	    _VOP(4, 1282),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavgsh",	    _VOP(4, 1346),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vavgsw",	    _VOP(4, 1410),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vrlb",	    _VOP(4,    4),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vrlh",	    _VOP(4,   68),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vrlw",	    _VOP(4,  132),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vslb",	    _VOP(4,  260),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vslh",	    _VOP(4,  324),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vslw",	    _VOP(4,  388),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsl",	    _VOP(4,  452),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsrb",	    _VOP(4,  516),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsrh",	    _VOP(4,  580),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsrw",	    _VOP(4,  644),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsr",	    _VOP(4,  708),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsrab",	    _VOP(4,  772),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsrah",	    _VOP(4,  836),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsraw",	    _VOP(4,  900),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vand",	    _VOP(4, 1028),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vandc",	    _VOP(4, 1092),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vor",	    _VOP(4, 1156),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vnor",	    _VOP(4, 1284),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"mfvscr",	    _OP(4,   770),  _IFORM_VX_2,   _IFLAG_AV_SPEC},
    {"mtvscr",	    _OP(4,   802),  _IFORM_VX_3,   _IFLAG_AV_SPEC},
    {"vmuloub",	    _VOP(4,    8),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmulouh",	    _VOP(4,   72),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmulosb",	    _VOP(4,  264),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmulosh",	    _VOP(4,  328),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmuleub",	    _VOP(4,  520),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmuleuh",	    _VOP(4,  584),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmulesb",	    _VOP(4,  776),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vmulesh",	    _VOP(4,  840),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsum4ubs",    _VOP(4, 1544),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsum4sbs",    _VOP(4, 1800),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsum4shs",    _VOP(4, 1608),  _IFORM_VX_1,   _IFLAG_AV_SPEC},
    {"vsum2sws",    _VOP(4, 1672),  _IFORM_VX_1,   _IFLAG_AV_SPEC},