dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

    0xfc00003f,		/* _IFORM_VA_1B	   77	vmaddfp			     */
    
    /* 440x5 and 85xx */
    0xfc00003e,		/* _IFORM_M_3	   78   isel			     */

    /* The following are for E500 (85xx), based on prelim manuals.
       The reserved bits are now don't cares instead of mandated zeros. */

    0xfc0007fe,         /* _IFORM_X_34     79   mbar (with MO field)         */
    0xfc0007fe,         /* _IFORM_X_35     80   wrteei                       */
    0xfc0007fc,         /* _IFORM_X_36     81   tlbivax                      */
    0xfc0007fe,         /* _IFORM_X_37     82   tlbsx                        */
    0xfc0007ff,         /* _IFORM_X_38     83   tlbre                        */
    0xfc0007ff,         /* _IFORM_XFX_5    84   mfpmr                        */
    0xfc0007ff,         /* _IFORM_XFX_6    85   mtpmr                        */
    0xfc0007f8,         /* _IFORM_EVS_1    86   evsel                        */
    0xfc0007ff,         /* _IFORM_EFX_1    87   efsadd                       */
    0xfc0007ff,         /* _IFORM_EFX_2    88   efscfsf                      */
    0xfc0007ff,         /* _IFORM_EFX_3    89   efsabs                       */
    0xfc0007ff,         /* _IFORM_EFX_4    90   efscmpeq                     */
    0xfc0007ff,         /* _IFORM_EVX_1    91   brinc                        */
    0xfc0007ff,         /* _IFORM_EVX_2    92   evfscfsf                     */
    0xfc0007ff,         /* _IFORM_EVX_3    93   evabs                        */
    0xfc0007ff,         /* _IFORM_EVX_4    94   evaddiw                      */
    0xfc0007ff,         /* _IFORM_EVX_5    95   evrlwi                       */
    0xfc0007ff,         /* _IFORM_EVX_6    96   evcmpeq                      */
    0xfc0007ff,         /* _IFORM_EVX_7    97   evsplatfi                    */
    0xfc0007ff,         /* _IFORM_EVX_8    98   evstddx                      */
    0xfc0007ff,         /* _IFORM_EVX_9    99   evstdh                       */
    0xfc0007ff,         /* _IFORM_EVX_10  100   evstwhe                      */
    0xfc0007ff,         /* _IFORM_EVX_11  101   evldd                        */
    0xfc0007ff,         /* _IFORM_EVX_12  102   evlhhesplat                  */
    0xfc0007ff,         /* _IFORM_EVX_13  103   evlwhe                       */
    0xfc0007ff          /* _IFORM_EVX_14  104   evsubifw                     */

#if	(!defined(HOST))
    ,(UINT32)NULL	/* mark the end of mask []			     */
#endif	/* HOST */
    };

/*

This structure contains the complete listing of the PowerPC commands.
Some implementation specific commands are also included, as well as
some simplified mnemonics. Simplified mnemonics have to be put in front.
The commands are the ones described in the PowerPC manuals.

Optional commands, present in only some implementations, are supported
on their respective target disassemblers, and on the host when connected
to a target which implements them.

The listing is made following the different forms (D, X, ...), as in
the PowerPC manual.

*/

LOCAL INST inst [] =
    {

/*  ascii       instruction bits    form name       classification flags      */
/*  -----       ----------------    ---------       --------------------      */

    /* the following instructions are simplified mnemonics */

    {"nop",      0x60000000,         _IFORM_SC_1,   0},	    /* ori r0,r0,0 */
    {"blr",      0x4e800020,         _IFORM_SC_1,   0},	    /* bclr   20,0 */
    {"blrl",	 0x4e800021,         _IFORM_SC_1,   0},     /* bclr   20,0 */
    {"bctr",     0x4e800420,         _IFORM_SC_1,   0},     /* bcctr  20,0 */
    {"bctrl",    0x4e800021,         _IFORM_SC_1,   0},     /* bcctrl 20,0 */
    {"bdzlr",    0x4e400020,         _IFORM_SC_1,   0},     /* bclr   18,0 */
    {"bdzlrl",   0x4e400021,         _IFORM_SC_1,   0},     /* bclrl  18,0 */
    {"bdnzlr",   0x4e000020,         _IFORM_SC_1,   0},     /* bclr   16,0 */
    {"bdnzlrl",  0x4e000021,         _IFORM_SC_1,   0},     /* bclrl  16,0 */
    {"li",       _OP(14,    0),      _IFORM_D_9,    0},     /* addi   RT,0,IM */
    {"lis",      _OP(15,    0),      _IFORM_D_9,    0},     /* addi   RT,0,IM */

    /* the following instructions are specific to the PPC400 family */
 
#if	(defined(HOST) || (CPU == PPC403) || (CPU==PPC405) || (CPU==PPC405F) || (CPU==PPC440))

    {"dccci",    _OP(31,  454),      _IFORM_X_22,    _IFLAG_4XX_SPEC},
    {"dcread",   _OP(31,  486),      _IFORM_X_1,     _IFLAG_4XX_SPEC},
    {"icbt",     _OP(31,  262),      _IFORM_X_22,    _IFLAG_4XX_SPEC},
    {"iccci",    _OP(31,  966),      _IFORM_X_22,    _IFLAG_4XX_SPEC},
    {"icread",   _OP(31,  998),      _IFORM_X_22,    _IFLAG_4XX_SPEC},
    {"mfdcr",    _OP(31,  323),      _IFORM_400_1,   _IFLAG_4XX_SPEC},
    {"mtdcr",    _OP(31,  451),      _IFORM_400_2,   _IFLAG_4XX_SPEC},
    {"rfci",     _OP(19,   51),      _IFORM_XL_4,    _IFLAG_4XX_SPEC},
    {"wrtee",    _OP(31,  131),      _IFORM_X_13,    _IFLAG_4XX_SPEC},
    {"wrteei",   _OP(31,  163),      _IFORM_400_3,   _IFLAG_4XX_SPEC},

#endif	/* HOST || PPC4xx */

    /* the following instructions are specific to the IBM 405 & 440 */

#if (defined(HOST) || (CPU == PPC405) || (CPU == PPC405F) || (CPU==PPC440))

    {"mulchw",  _OP( 4,  168), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},
    {"mulchwu", _OP( 4,  136), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},
    {"mulhhw",  _OP( 4,   40), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},
    {"mulhhwu", _OP( 4,    8), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},
    {"mullhw",  _OP( 4,  424), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},
    {"mullhwu", _OP( 4,  392), _IFORM_XO_2, _IFLAG_RC | _IFLAG_MAC},

    {"macchw",  _OP( 4,  172), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"macchws", _OP( 4,  236), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"macchwsu",_OP( 4,  204), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"macchwu", _OP( 4,  140), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"machhw",  _OP( 4,   44), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"machhws", _OP( 4,  108), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"machhwsu",_OP( 4,   76), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"machhwu", _OP( 4,   12), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"maclhw",  _OP( 4,  428), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"maclhws", _OP( 4,  492), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"maclhwsu",_OP( 4,  460), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"maclhwu", _OP( 4,  396), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmacchw", _OP( 4,  174), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmacchws",_OP( 4,  238), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmachhw", _OP( 4,   46), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmachhws",_OP( 4,  110), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmaclhw", _OP( 4,  430), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},
    {"nmaclhws",_OP( 4,  494), _IFORM_XO_1, _IFLAG_RC | _IFLAG_OE | _IFLAG_MAC},

    {"tlbsx",   _OP(31,  914), _IFORM_405_SX,  _IFLAG_RC | _IFLAG_4XTLB},
    {"tlbre",   _OP(31,  946), _IFORM_405_TLB, _IFLAG_4XTLB},
    {"tlbwe",   _OP(31,  978), _IFORM_405_TLB, _IFLAG_4XTLB},

#endif	/* HOST || (CPU==PPC405) || (CPU==PPC405F) || (CPU==PPC440) */

	/* Specific to the PPC440 */
#if	(defined(HOST) || (CPU == PPC440))
    {"icbt",	_OP(31,   22), _IFORM_X_22, _IFLAG_440_SPEC},
    {"dlmzb",	_OP(31,   78), _IFORM_X_8,  _IFLAG_RC | _IFLAG_440_SPEC},
#endif	/* HOST || CPU == PPC440 */

	/*
	 * Specific to the PPC440x5 core.  No need to explicitly test CPU,
	 * since PPC_440x5 will not be defined unless CPU == PPC440.  Host
	 * will disassemble for all 440 since at present there is no way
	 * for it to know about a CPU_VARIANT.
	 */
#if	(defined(HOST) || defined(PPC_440x5))
    {"isel",	_OP(31,   15), _IFORM_M_3,  _IFLAG_440_SPEC},
    {"rfmci",	_OP(19,   38), _IFORM_XL_4, _IFLAG_440_SPEC},
#endif	/* HOST || PPC_440x5 */

    /* the following instructions are specific to the PPC603 and PPCEC603 */

#if	(defined(HOST) || (CPU == PPC603) || (CPU == PPCEC603))

    {"tlbld",    _OP(31,  978),     _IFORM_X_2,     _IFLAG_603_SPEC},
    {"tlbli",    _OP(31, 1010),     _IFORM_X_2,     _IFLAG_603_SPEC},

#endif	/* PPC603 PPCEC603 */

    /* the following instructions are specific to the PPC85XX (E500) */

#if	(defined(HOST) || (CPU == PPC85XX))
    {"bbelr",    _OP(31,  550),     _IFORM_X_23,    _IFLAG_E500_SPEC},
    {"bblels",   _OP(31,  518),     _IFORM_X_23,    _IFLAG_E500_SPEC},
    {"dcblc",    _OP(31,  390),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"dcbtls",   _OP(31,  166),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"dcbtstls", _OP(31,  134),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"icblc",    _OP(31,  230),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"icbt",     _OP(31,   22),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"icbtls",   _OP(31,  486),     _IFORM_X_21,    _IFLAG_E500_SPEC},
    {"isel",	 _OP(31,   15),     _IFORM_M_3,     _IFLAG_E500_SPEC},
    {"msync",    _OP(31,  598),     _IFORM_X_23,    _IFLAG_E500_SPEC},
    {"mbar",     _OP(31,  854),     _IFORM_X_34,    _IFLAG_E500_SPEC},
    {"tlbivax",  _OP(31,  786),     _IFORM_X_36,    _IFLAG_E500_SPEC},
    {"tlbre",    _OP(31,  946),     _IFORM_X_38,    _IFLAG_E500_SPEC},
    {"tlbsx",    _OP(31,  914),     _IFORM_X_37,    _IFLAG_E500_SPEC},
    {"tlbwe",    _OP(31,  978),     _IFORM_X_38,    _IFLAG_E500_SPEC},
    {"rfci",     _OP(19,   51),     _IFORM_XL_4,    _IFLAG_E500_SPEC},
    {"rfmci",    _OP(19,   38),     _IFORM_XL_4,    _IFLAG_E500_SPEC},
    {"wrtee",    _OP(31,  131),     _IFORM_X_13,    _IFLAG_E500_SPEC},
    {"wrteei",   _OP(31,  163),     _IFORM_X_35,    _IFLAG_E500_SPEC},
    {"mfpmr",    _OP(31,  334),     _IFORM_XFX_5,   _IFLAG_E500_SPEC},
    {"mtpmr",    _OP(31,  462),     _IFORM_XFX_6,   _IFLAG_E500_SPEC},
#endif	/* PPC85XX */

    /* the following instructions are generic to PowerPC */

    {"b",        _OP(18,    0),     _IFORM_I_1,     _IFLAG_AA | _IFLAG_LK},
    {"bc",       _OP(16,    0),     _IFORM_B_1,     _IFLAG_AA | _IFLAG_LK},
    {"sc",       _OP(17,    1),     _IFORM_SC_1,    0},

    {"addi",     _OP(14,    0),     _IFORM_D_2,     0},
    {"addic",    _OP(12,    0),     _IFORM_D_2,     0},
    {"addic.",   _OP(13,    0),     _IFORM_D_2,     0},
    {"addis",    _OP(15,    0),     _IFORM_D_2,     0},
    {"andi.",    _OP(28,    0),     _IFORM_D_4,     0},
    {"andis.",   _OP(29,    0),     _IFORM_D_4,     0},
    {"cmpi",     _OP(11,    0),     _IFORM_D_5,     0},
    {"cmpli",    _OP(10,    0),     _IFORM_D_6,     0},
    {"lbz",      _OP(34,    0),     _IFORM_D_1,     0},
    {"lbzu",     _OP(35,    0),     _IFORM_D_1,     0},
    {"lfd",      _OP(50,    0),     _IFORM_D_8,     0},
    {"lfdu",     _OP(51,    0),     _IFORM_D_8,     0},
    {"lfs",      _OP(48,    0),     _IFORM_D_8,     0},
    {"lfsu",     _OP(49,    0),     _IFORM_D_8,     0},
    {"lha",      _OP(42,    0),     _IFORM_D_1,     0},
    {"lhau",     _OP(43,    0),     _IFORM_D_1,     0},
    {"lhz",      _OP(40,    0),     _IFORM_D_1,     0},
    {"lhzu",     _OP(41,    0),     _IFORM_D_1,     0},
    {"lmw",      _OP(46,    0),     _IFORM_D_1,     0},
    {"lwz",      _OP(32,    0),     _IFORM_D_1,     0},
    {"lwzu",     _OP(33,    0),     _IFORM_D_1,     0},
    {"mulli",    _OP( 7,    0),     _IFORM_D_2,     0},
    {"ori",      _OP(24,    0),     _IFORM_D_4,     0},
    {"oris",     _OP(25,    0),     _IFORM_D_4,     0},
    {"stb",      _OP(38,    0),     _IFORM_D_3,     0},
    {"stbu",     _OP(39,    0),     _IFORM_D_3,     0},
    {"stfd",     _OP(54,    0),     _IFORM_D_8,     0},
    {"stfdu",    _OP(55,    0),     _IFORM_D_8,     0},
    {"stfs",     _OP(52,    0),     _IFORM_D_8,     0},
    {"stfsu",    _OP(53,    0),     _IFORM_D_8,     0},
    {"sth",      _OP(44,    0),     _IFORM_D_3,     0},
    {"sthu",     _OP(45,    0),     _IFORM_D_3,     0},
    {"stmw",     _OP(47,    0),     _IFORM_D_3,     0},
    {"stw",      _OP(36,    0),     _IFORM_D_3,     0},
    {"stwu",     _OP(37,    0),     _IFORM_D_3,     0},
    {"subfic",   _OP( 8,    0),     _IFORM_D_2,     0},
    {"twi",      _OP( 3,    0),     _IFORM_D_7,     0},
    {"xori",     _OP(26,    0),     _IFORM_D_4,     0},
    {"xoris",    _OP(27,    0),     _IFORM_D_4,     0},

    {"and",      _OP(31,   28),     _IFORM_X_8,     _IFLAG_RC},
    {"andc",     _OP(31,   60),     _IFORM_X_8,     _IFLAG_RC},
    {"cmp",      _OP(31,    0),     _IFORM_X_16,    0},
    {"cmpl",     _OP(31,   32),     _IFORM_X_16,    0},
    {"cntlzw",   _OP(31,   26),     _IFORM_X_11,    _IFLAG_RC},
    {"dcbf",     _OP(31,   86),     _IFORM_X_22,    0},
    {"dcbi",     _OP(31,  470),     _IFORM_X_22,    0},
    {"dcbst",    _OP(31,   54),     _IFORM_X_22,    0},
    {"dcbt",     _OP(31,  278),     _IFORM_X_22,    0},