dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

/* dsmPpc.c - PowerPC disassembler */

/* Copyright 1994-2003 Wind River Systems, Inc. */

#include "copyright_wrs.h"

/*
modification history
--------------------
01g,16sep03,mil  Fixed build problem for host mcore target.
01f,16jun03,mil  Added E500 instructions.
01e,10jun03,tpw  Merge T2.2 CP1 to E500
01d,23jan03,pch  Add isel and rfmci for 440x5 core (440GX)
01d,03aug02,pcs  Add support for PPC85XX and make it the same as PPC603 for
                 the present.
01c,29nov01,pch  SPR 71662: improve formatting consistency
01b,29oct01,pch  Add host-side debugging; retrieve target info before
		 calling dsmFind() (which needs it :)
01a,18sep01,pch  created by merging target/src/arch/ppc/dsmLib.c vn 01o
		 and host/src/tgtsvr/disassembler/dsmPpc.c vn 02r
		 Also added selective handling of processor-specific SPR's
		 and instructions in the host disassembler based on the
		 cpuType of the currently-connected target.

Following are the history entries from the merged files

    07sep01,pch  Add PPC440 operations & registers, cleanup; fix for SPR 70249.
    01jun01,dtr  Instructions dst,dstt,dstst,dststt are mixed up.
                 Instruction name change vrsqte -> vrsqrte.
                 New IFORM_VA1B for vmaddfp,vnmsubfp vB,vC swapped vC,vB. 

    30may01,dtr  Removing debug.
    29may01,dtr  Removing duplicated mask.
    30apr01,dtr  Correcting merge errors.
    27mar01,dtr  Replacing #ifdef SP7400 with  PPC604 && WRS_ALTIVEC_SUPPORT.
    15feb01,jrs  Fix masking for mulch insns.
    14feb01,jrs  Add mulc class instructions (MAC).
    14feb01,jrs  Add MMU instructions.
    14feb01,jrs  Clean up SPR registers for IBM 405.
    09dec00,jrs  Fix WS field map
    08dec00,jrs  Fix register map for dcr's.
    07dec00,dtr  Support for Altivec Instruction Set.
    04dec00,jrs  Add 405-specific target register mappings.
    30nov00,jrs  Add IBM 405 MAC and TLB instructions.
    17nov00,jrs  Add PPC405 changes.
    14sep98,fle  changed output string format
    18aug98,tpr  added PowerPC EC 603 support.
    20apr98,fle  removed appending disassembled instruction with <CR> to
                 proceed it in host/src/tgtsvr/server/tsDisassemble.c
    04mar98,fle  warnings eradication
    03sep97,fle  Adding the WTX_MEM_DISASSEMBLE service
		 + put options for returning (or not) instructions address and
		   instructions opcodes.
    26jul96,tam  cleanup. added simplified mnemonics.
    07jun96,kkk  added endian argument to dsmXXXInst and dsmXXXNbytes.
    18jun96,pr   cleanup.
	    tam  added simplified mnemonics li and lis. Fixed decoding of DCRs.
    28mar96,tam  fixed decodeSpecial() to use regList[] instead of spr[].
		 added {} in dcr, added missing declarations for DMACCx.
    27mar96,ms   added in all the #if CPU==XXX stuff.
    24jan96,elp  fixed cross-endian disassembly.
    02jan96,elp  adapted for Tornado.
    18apr95,caf  fixed floating point loads and stores.
    08feb95,caf  added PPC403 support, cleaned up SPR handling.
    29jan95,caf  fixed decoding of absolutes and immediates, changed "nop",
		 added "blr".
    22aug94,caf  created, based on version 03l of src/arch/mc68k/dsmLib.c.
*/

/*
DESCRIPTION

This library contains everything necessary to print PowerPC object code in
assembly language format. The format described below are taken from the
PowerPC manual. Some discrepancies can occur, since the formats are also
used for the printout layout. Some of the formats are the same for commands
that refer to both floating point and non floating point registers.  In
such cases the format has been split so that the respective definitions
could be used in the printout layout.

In the target server (which runs on the host), the programming
interface is via dsmPpcInstGet(). In the target shell, the interface
is via dsmInst().  Each of these entry points prints a single
disassembled instruction.

To disassemble from the shell, use l(), which calls this
library to do the actual work.  See dbgLib() for details.

INCLUDE FILE: dsmPpc.h

SEE ALSO: windSh and dbgLib
*/

/* includes */

#if	defined(HOST)

#include <stdlib.h>
#include <string.h>
#include "host.h"
#include "dsmPpc.h"
#include "wtx.h"
#include "tgtlib.h"

# ifdef CPU
# include "cputypes.h"
# else /* CPU */
# define CPU 0
# include "cputypes.h"
# undef CPU
# endif	/* CPU */

#else	/* HOST */

#include "vxWorks.h"
#include "errnoLib.h"
#include "dsmLib.h"

#endif	/* HOST */

#include "stdio.h"

/* locals */

#if	defined(HOST)
/* Host knows how to disassemble all types, but customizes for current target */
LOCAL UINT32 targetCpuType = 0;		/* CPU type number, from agent */
LOCAL UINT32 targetCoProc = 0;		/* hasCoprocessor field */
LOCAL UINT16 targetInstFlags = 0;	/* flags for supported instructions */
#endif	/* HOST */

/*

This structure contains the masks to be used for recognizing the op code
for the different commands. It is based on the form description given in
the PowerPC manual. Some implementation specific form are also included,
as well as some simplified mnemonics. Some of the form have the same
mask but are addressing different registers. In some cases, the same form
has been doubled (thus introducing an extra form with respect to the ones
described in the manual) to distinguish between operations on floating point
and general registers.

XXX - _IFORM_XO_2 is a misnomer.  These instructions
XXX - are actually form X, not form XO.

*/

LOCAL UINT32 mask [] =
    {

/*  instruction mask       form name       #    example instruction          */
/*  ----------------       ---------       -    -------------------          */

    0xfc000000,         /* _IFORM_I_1      0    b                            */
    0xfc000000,         /* _IFORM_B_1      1    bc                           */
    0xffffffff,         /* _IFORM_SC_1     2    sc                           */
    0xfc000000,         /* _IFORM_D_1      3    lwz                          */
    0xfc000000,         /* _IFORM_D_2      4    addi                         */
    0xfc000000,         /* _IFORM_D_3      5    stw                          */
    0xfc000000,         /* _IFORM_D_4      6    andi.                        */
    0xfc400000,         /* _IFORM_D_5      7    cmpi                         */
    0xfc400000,         /* _IFORM_D_6      8    cmpli                        */
    0xfc000000,         /* _IFORM_D_7      9    twi                          */
    0xfc000000,         /* _IFORM_D_8      10   stfd                         */
    0xfc0007ff,         /* _IFORM_X_1      11   lwzx                         */
    0xffff07ff,         /* _IFORM_X_2      12   tlbie                        */
    0xfc1f07ff,         /* _IFORM_X_3      13   mfsrin                       */
    0xfc1f07fe,         /* _IFORM_X_4      14   fabs                         */
    0xfc1fffff,         /* _IFORM_X_5      15   mfcr                         */
    0xfc1ffffe,         /* _IFORM_X_6      16   mffs                         */
    0xfc10ffff,         /* _IFORM_X_7      17   mfsr                         */
    0xfc0007fe,         /* _IFORM_X_8      18   and                          */
    0xfc0007ff,         /* _IFORM_X_9      19   stwcx.                       */
    0xfc0007ff,         /* _IFORM_X_10     20   stwx                         */
    0xfc00fffe,         /* _IFORM_X_11     21   cntlzw                       */
    0xfc1f07ff,         /* _IFORM_X_12     22   mtsrin                       */
    0xfc1fffff,         /* _IFORM_X_13     23   mtmsr                        */
    0xfc10ffff,         /* _IFORM_X_14     24   mtsr                         */
    0xfc0007fe,         /* _IFORM_X_15     25   srawi                        */
    0xfc4007ff,         /* _IFORM_X_16     26   cmp                          */
    0xfc6007ff,         /* _IFORM_X_17     27   fcmpo                        */
    0xfc63ffff,         /* _IFORM_X_18     28   mcrfs                        */
    0xfc7fffff,         /* _IFORM_X_19     29   mcrxr                        */
    0xfc7f0ffe,         /* _IFORM_X_20     30   mtfsfi                       */
    0xfc0007ff,         /* _IFORM_X_21     31   tw                           */
    0xffe007ff,         /* _IFORM_X_22     32   dcbz                         */
    0xffffffff,         /* _IFORM_X_23     33   sync                         */
    0xfc0007ff,         /* _IFORM_X_24     34   stfdux                       */
    0xfc0007fe,         /* _IFORM_X_25     35   mtfsb0                       */
    0xfc0007ff,         /* _IFORM_X_26     36   lswi                         */
    0xfc0007ff,         /* _IFORM_X_27     37   stswi                        */
    0xfc00fffe,         /* _IFORM_XL_1     38   bcctr                        */
    0xfc0007ff,         /* _IFORM_XL_2     39   crand                        */
    0xfc63ffff,         /* _IFORM_XL_3     40   mcrf                         */
    0xffffffff,         /* _IFORM_XL_4     41   rfi                          */
    0xfc0007ff,         /* _IFORM_XFX_1    42   mfspr                        */
    0xfc100fff,         /* _IFORM_XFX_2    43   mtcrf                        */
    0xfc0007ff,         /* _IFORM_XFX_3    44   mftb                         */
    0xfc0007ff,         /* _IFORM_XFX_4    45   mtspr                        */
    0xfe0107fe,         /* _IFORM_XFL_1    46   mtfsf                        */
    0xfc0003fe,         /* _IFORM_XO_1     47   add                          */
    0xfc0007fe,         /* _IFORM_XO_2     48   mulhw                        */
    0xfc00fbfe,         /* _IFORM_XO_3     49   addme                        */
    0xfc0007fe,         /* _IFORM_A_1      50   fadd                         */
    0xfc00003e,         /* _IFORM_A_2      51   fmadd                        */
    0xfc00f83e,         /* _IFORM_A_3      52   fmul                         */
    0xfc1f07fe,         /* _IFORM_A_4      53   fres                         */
    0xfc000000,         /* _IFORM_M_1      54   rlwimi                       */
    0xfc000000,         /* _IFORM_M_2      55   rlwnm                        */
    0xfc1f0000,         /* _IFORM_D_9      56   li                           */

    /* the following instructions are specific to the PPC400 family */

    0xfc0007ff,         /* _IFORM_400_1    57   mfdcr                        */
    0xfc0007ff,         /* _IFORM_400_2    58   mtdcr                        */
    0xffff7fff,         /* _IFORM_400_3    59   wrteei                       */
    0xfc0007fe,		/* _IFORM_405_TLB  60   tlbre, tlbwe                 */
    0xfc0007fe,		/* _IFORM_405_SX   61   tlbsx                        */

    /* the following are for altivec support */

    0xfc00003f,		/* _IFORM_VA_1	   62	vmhaddshs		     */
    0xfc00043f,		/* _IFORM_VA_2	   63   vsldoi      		     */
    0xfc0007ff,		/* _IFORM_VX_1     64	vaddubm 		     */
    0xfc1fffff,		/* _IFORM_VX_2     65	mfvscr  		     */
    0xffff07ff,		/* _IFORM_VX_3     66	mtvscr  		     */
    0xfc1f07ff,		/* _IFORM_VX_4     67	vrefp   		     */
    0xfc0007ff,		/* _IFORM_VX_5     68	vcfux   		     */
    0xfc00ffff,		/* _IFORM_VX_6     69	vspltisb 		     */
    0xfc0007ff,		/* _IFORM_X_28	   70	lvebx			     */
    0xfc0007ff,		/* _IFORM_X_29	   71	stvebx			     */
    0xfc8007ff,		/* _IFORM_X_30	   72	dstt			     */
    0xfec007ff,		/* _IFORM_X_31	   73	dst			     */
    0xfc9fffff,		/* _IFORM_X_32	   74	dssall			     */
    0xfe9fffff,		/* _IFORM_X_33	   75	dss			     */
    0xfc0003ff,		/* _IFORM_VXR_1	   76	vcmpbfp			     */