cachearchlib.c

VxWorks BSP框架源代码包含头文件和驱动

	return (ERROR);				/* invalid cache */

    if (!cacheIsOn (cache))			/* cache already on? */
	cacheSet (cache, C_ENABLE, C_ENABLE);	/* turn the cache on */

    if (cache == DATA_CACHE)
	{
	cacheDataEnabled = TRUE;
	cacheFuncsSet ();
	}

    return (OK);
    }

/*******************************************************************************
*
* cacheArchDisable - disable a 68K cache
*
* This routine disables the specified 68K instruction or data cache.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*
* NOMANUAL
*/

STATUS cacheArchDisable
    (
    CACHE_TYPE	cache		/* cache to disable */
    )
    {
    if (cacheProbe (cache) != OK)
	return (ERROR);				/* invalid cache */

    if (cacheIsOn (cache))			/* already off? */
	{
#if ((CPU == MC68020) || (CPU == MC68030))
	cacheSet (cache, 0, C_ENABLE);		/* disable the cache */
	cacheSet (cache, C_CLR, C_CLR); 	/* invalidate cache entries */
#elif ((CPU==MC68040) || (CPU==MC68060) || (CPU==MC68LC040))

	switch (cache)
	    {
	    case DATA_CACHE:
		cache040DataDisable ();		/* disable/push/invalidate */
		break;

#if (CPU==MC68060)
	    case BRANCH_CACHE:
		cacheSet (cache, 0, C_ENABLE);	/* disable branch cache */
		cacheBranchInv ();		/* invalidate B-cache entries */
		break;
#endif /* (CPU==MC68060) */

	    case INSTRUCTION_CACHE:
		cacheSet (cache, 0, C_ENABLE);	/* disable instruction cache */
		cacheCINV (INSTRUCTION_CACHE, CACHE_ALL, 0x0);	/* inv cache */	
		break;

	    default :
		/* cacheProbe returns ERROR */
	    }
#endif
	}

    if (cache == DATA_CACHE)
	{
	cacheDataEnabled = FALSE;		/* data cache is off */
	cacheFuncsSet ();			/* update data function ptrs */
	}

    return (OK);
    }

/*******************************************************************************
*
* cacheArchLock - lock entries in a 68K cache
*
* This routine locks all entries in the specified 68K cache.  Only the 68020, 
* 68030 and 68060 allow cache locking.  The <bytes> argument must be set 
* to ENTIRE_CACHE.
*
* The 68060 banch cache can not be locked so if <cache> is BRANCH_CACHE 
* the function will return ERROR.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*
* NOMANUAL
*/

STATUS cacheArchLock
    (
    CACHE_TYPE	cache, 		/* cache to lock */
    void *	address,	/* address to lock */
    size_t	bytes		/* bytes to lock (ENTIRE_CACHE) */
    )
    {
    if (cacheProbe (cache) != OK)
	return (ERROR);				/* invalid cache */

#if ((CPU == MC68020) || (CPU == MC68030) || (CPU == MC68060))

    if (bytes != ENTIRE_CACHE)
	return (ERROR);				/* invalid operation */

#if (CPU == MC68060)
    if (cache == BRANCH_CACHE)
	return (ERROR);				/* invalid operation */
#endif /* (CPU == MC68060) */

    cacheSet (cache, C_FREEZE, C_FREEZE);	/* diddle the CACR bit */
    return (OK);

#elif (CPU == MC68040 || CPU == MC68LC040)
    errno = S_cacheLib_INVALID_CACHE;		/* set errno */
    return (ERROR);				/* no cache */
#endif
    }

/*******************************************************************************
*
* cacheArchUnlock - unlock a 68K cache
*
* This routine unlocks all entries in the specified 68K cache.  Only the 
* 68020, 68030 and 68060 allow cache locking.  The <bytes> argument must be 
* set to ENTIRE_CACHE.
*
* The 68060 banch cache can not be unlocked so if <cache> is BRANCH_CACHE 
* the function will return ERROR.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*
* NOMANUAL
*/

STATUS cacheArchUnlock
    (
    CACHE_TYPE	cache, 		/* cache to unlock */
    void *	address,	/* address to unlock */
    size_t	bytes		/* bytes to unlock (ENTIRE_CACHE) */
    )
    {
    if (cacheProbe (cache) != OK)
	return (ERROR);				/* invalid cache */

#if ((CPU == MC68020) || (CPU == MC68030) || (CPU == MC68060))

    if (bytes != ENTIRE_CACHE)
	return (ERROR);				/* invalid operation */

#if (CPU == MC68060)
    if (cache == BRANCH_CACHE)
	return (ERROR);				/* invalid operation */
#endif /* (CPU == MC68060) */

    cacheSet (cache, 0, C_FREEZE);		/* diddle the CACR bit */
    return (OK);

#elif (CPU == MC68040 || CPU == MC68LC040)
    errno = S_cacheLib_INVALID_CACHE;		/* set errno */
    return (ERROR);				/* no cache */
#endif
    }

/*******************************************************************************
*
* cacheArchClear - clear all entries from a 68K cache
*
* This routine clears some or all entries from the specified 68K cache.  
* 
* For the MC68060 processor, when the instruction cache is cleared (invalidated)* the branch cache is also invalidated by the hardware. One line in the branch
* cache cannot be invalidated so each time the branch cache is entirely
* invalidated.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*
* NOMANUAL
*/

STATUS cacheArchClear
    (
    CACHE_TYPE	cache, 		/* cache to clear */
    void *	address,	/* address to clear */
    size_t	bytes		/* bytes to clear */
    )
    {
#if (CPU == MC68060)
    int cacr;			/* cache control register value */
#endif /* (CPU == MC68060) */

    if (cacheProbe (cache) != OK)
	return (ERROR);				/* invalid cache */

#if ((CPU == MC68020) || (CPU == MC68030))

    if (bytes == ENTIRE_CACHE)
        {
	cacheSet (cache, C_CLR, C_CLR);		/* invalidate all cache */
	}
    else
	{
	bytes += (size_t) address;
	address = (void *) ((UINT) address & ~(4 - 1));

	do  {
	    cacheCAARSet ((void *) ((UINT) address & C_INDEX_MASK));
	    cacheSet (cache, C_CLR_ENTRY, C_CLR_ENTRY);
	    address = (void *) ((UINT) address + 4);
	    } while ((size_t) address < bytes);
	}

    return (OK);

#elif ((CPU == MC68040) || (CPU == MC68060) || (CPU == MC68LC040))

#if (CPU == MC68060)
    if (cache == BRANCH_CACHE)
	{
	cacheBranchInv ();			/* invalidate branch cache */
	return (OK);
	}

    cacr = cacheCACRGet ();			/* get CACR value */
    cacheCACRSet (cacr & ~C_CACR_DPI); 		/* enable CPUSH invalidation */
#endif /* (CPU == MC68060) */

    if (bytes == ENTIRE_CACHE)
        {
	cacheCPUSH (cache, CACHE_ALL, 0x0);	/* push/invalidate all cache */
	}
    else
	{
	bytes += (size_t) address;
	address = (void *) ((UINT) address & ~(_CACHE_ALIGN_SIZE - 1));

	do  {
	    cacheCPUSH (cache, CACHE_LINE, (void *) address);
	    address = (void *) ((UINT) address + _CACHE_ALIGN_SIZE);
	    } while ((size_t) address < bytes);
	}

    cache040WriteBufferFlush ();		/* flush write buffer */

#if (CPU == MC68060)
	cacheCACRSet (cacr);			/* restore CACR value */
#endif /* (CPU == MC68060) */

    return (OK);
#endif
    }

/*******************************************************************************
*
* cacheArchClearEntry - clear an entry from a 68K cache
*
* This routine clears a specified entry from the specified 68K cache.
*
* For 68040 processors, this routine clears the cache line from the cache
* in which the cache entry resides.
*
* For the MC68060 processor, when the instruction cache is cleared (invalidated)* the branch cache is also invalidated by the hardware. One line in the branch
* cache cannot be invalidated so each time the branch cache is entirely
* invalidated.
*
* RETURNS: OK, or ERROR if the cache type is invalid or the cache control
* is not supported.
*/

STATUS cacheArchClearEntry
    (
    CACHE_TYPE	cache,		/* cache to clear entry for */
    void *	address		/* entry to clear */
    )
    {
#if (CPU == MC68060)
    int cacr;			/* cache control register value */
#endif /* (CPU == MC68060) */

    if (cacheProbe (cache) != OK)
	return (ERROR);				/* invalid cache */

#if (CPU == MC68060)
    if (cache == BRANCH_CACHE)
	{
	cacheBranchInv ();			/* invalidate branch cache */
	return (OK);
	}

    cacr = cacheCACRGet ();			/* get CACR value */
    cacheCACRSet (cacr & ~C_CACR_DPI);		/* enable CPUSH invalidation */
#endif /* (CPU == MC68060) */

#if ((CPU == MC68020) || (CPU == MC68030))
    cacheCAARSet (address);			/* address to invalidate */
    cacheSet (cache, C_CLR_ENTRY, C_CLR_ENTRY); /* invalidate cache entries */
#elif ((CPU == MC68040) || (CPU == MC68060) || (CPU == MC68LC040))
    cacheCPUSH (cache, CACHE_LINE, address);	/* push/invalidate entry */
    cache040WriteBufferFlush ();		/* flush write buffer */
#endif

#if (CPU == MC68060)
	cacheCACRSet (cacr);			/* restore CACR value */
#endif /* (CPU == MC68060) */

    return (OK);
    }

/*******************************************************************************
*
* cacheArchDmaMalloc - allocate a cache-safe buffer
*
* This routine attempts to return a pointer to a section of memory
* that will not experience cache coherency problems.  This routine
* is only called when MMU support is available 
* for cache control.
*
* INTERNAL
* We check if the cache is actually on before allocating the memory.  It
* is possible that the user wants Memory Management Unit (MMU)
* support but does not need caching.
*
* RETURNS: A pointer to a cache-safe buffer, or NULL.
*
* SEE ALSO: cacheArchDmaFree(), cacheDmaMalloc()
*
* NOMANUAL
*/

void *cacheArchDmaMalloc 
    (
    size_t      bytes			/* size of cache-safe buffer */
    )
    {
    void *pBuf;
    int	  pageSize;

    if (!cacheIsOn (DATA_CACHE))	/* cache is off just allocate buffer */
	{
	pBuf = malloc (bytes);
	return (pBuf);
	}