dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

/* dsmLib.c - 680X0 disassembler */

/* Copyright 1984-1994 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
03o,31oct94,kdl  merge cleanup.
03n,26oct94,tmk  added MC68LC040 support
03m,30may94,tpr  added MC68060 cpu support.
03m,13sep94,ism  fixed bug in move.l (SPR #1311)
03l,16sep92,jmm  added default to case statement in prtArgs to fix warning msg
03k,18sep92,jmm  changed commas in register lists to slashes
03j,17sep92,jmm  fixed disassembly of floating point instructions (spr 1521)
                 fixed fmovem arg list, changed (f)movem to display ranges
03i,18jul92,smb  Changed errno.h to errnoLib.h.
03h,26may92,rrr  the tree shuffle
03g,20jan92,shl  ANSI cleanup.
03f,04oct91,rrr  passed through the ansification filter
                  -changed functions to ansi style
		  -fixed #else and #endif
		  -changed VOID to void
		  -changed copyright notice
03e,28aug91,shl  added support for MC68040's new and modified instruction set.
03d,05apr91,jdi	 documentation -- removed header parens and x-ref numbers;
		 doc review by dnw.
03c,01apr91,yao  fixed bug for confusion of ADDX and ADD.L instructions(same
		 with SUB.L and SUBX).
03b,06mar91,jaa	 documentation cleanup.
03a,25oct90,yao  added MMU instructions. document.
02p,10aug90,dnw  added forward declarations of void functions.
02o,30may90,yao  changed to compare the first two words of instructions.
		 added effective address mode check to dsmFind ().
		 added DIVSL and DIVUL.
		 deleted findTwoWord () and findFpp (), deleted table
		 instTwo [] and instFpp [].
		 fixed excess comma's for move multiple instructions.
		 consistently used 0x instead of $ for constants.
02n,14mar90,jdi  documentation cleanup.
02m,30may88,dnw  changed to v4 names.
02l,26oct87,hin  Fixed bug, when base displacement was used without base
		 register, instruction length was wrong.
                 Added 68881 instructions.
02k,14sep87,llk  Fixed bug.  itShift instructions weren't handled correctly.
		 Split itShift into itRegShift and itMemShift.
02j,30jul87,llk  Fixed bug.  "PC indirect with index" was not handled correctly
		 for cases where there was no memory indirection.
02i,23mar87,jlf  documentation.
02h,09feb87,llk  Fixed bug.  ASL (and ASR) was displaying "ASL 0" for "ASL 8".
02g,21dec86,dnw  changed to not get include files from default directories.
02f,19dec86,llk  Fixed bug.  Collision occurred between AND and EXG.
02e,03dec86,ecs  Fixed bug in dsmPrint that caused 5-word instructions to
		 take up 2 lines.
02d,26may86,llk	 Got rid of lint introduced in 02a.
02c,23may86,llk	 Fixed bug.  CMPA was disassembled as CMPM.
02b,08apr86,llk	 Fixed bug introduced in 02a.  Negative displacements
		 of branch instructions not printed correctly.
02a,03apr86,llk	 Added 68020 instructions, reordered inst [] table by the
		 number of bits in an instruction's mask.  Added two word
		 instruction handling.  Added the routines mode6And7Words,
		 prOffWid, prIndirectIndex, prDisplace, findTwoWord.
		 Added the extension parameter to modeNwords.  Enable
		 printing of unlimited number of words per instruction.
		 Corrected spelling of "dissasembler".
		 Still needs better handling of two word instructions.
01q,20jul85,jlf  documentation.
01p,12jun85,rdc  added 68010 instructions.
01o,11nov84,jlf  Fixed shift instructions to work right.
01n,11nov84,jlf  Made EXT be its own type.
01m,20sep84,ecs&jlf  Added dsmData.
		 Changed dsmPrint to print unknown instructions as data.
		 Fixed bug in printing cmpa (introduced in 01k).
		 Made CMPM be its own type.
01l,18sep84,jlf  Removed l from the description.
01k,17sep84,jlf  Separated out adda and suba from add and sub, to fix a bug
		 with printing adda's sometimes.
01j,10sep84,ecs  Removed l, lPrtAddress, and nxtToDsm to dbgLib.c.
01g,09sep84,jlf  Added dsmNbytes, got rid of GLOBAL.
01h,06aug84,jlf  Added copyright notice, and some comments.
01g,30aug84,jlf  Fixed bug that sometimes caused ADDX and ADD.L to get
		 confused (and same for SUBX).
01f,23aug84,ecs  Changed nxtToDsm to GLOBAL.
01e,16aug84,jlf  Fixed bug in printing DBcc and Scc instructions, by adding
		 new instruction types itDb and itScc.  Changed some
		 routines to accept the address of the instruction they
		 are disassembling as a parameter, rather than just looking
		 at the pointer to the instruction.  This will make it
		 easier to make this stuff work under unix.
01d,07aug84,ecs  Added call to setStatus to dsmFind.
		 Split instruction type definitions and definition of structure
		 INST off to dsmLib.h.
01c,24jul84,ecs&jlf  Appeased lint and fixed subq bug (didn't print dest.).
01b,16jul84,jlf  Minor bug fixes.  Made unlk instruction use A reg (bug
		 had D reg) and made long immediate operands print right,
		 even if low order word is 0.
01a,29jun84,jlf	 written
*/

/*
This library contains everything necessary to print 680x0 object code in
assembly language format.  The disassembly is done in Motorola format.

The programming interface is via dsmInst(), which prints a single disassembled
instruction, and dsmNbytes(), which reports the size of an instruction.

To disassemble from the shell, use l(), which calls this
library to do the actual work.  See dbgLib() for details.

INCLUDE FILE: dsmLib.h

SEE ALSO: dbgLib
*/

#include "vxWorks.h"
#include "dsmLib.h"
#include "symLib.h"
#include "string.h"
#include "stdio.h"
#include "errnoLib.h"

#define LONGINT	 	0
#define SINGLEREAL	1
#define EXTENDEDREAL	2
#define PACKEDDECIMAL	3
#define WORDINT		4
#define DOUBLEREAL	5
#define BYTEINT		6

/* forward static functions */

static INST *dsmFind (USHORT binInst [ ]);
static void dsmPrint (USHORT binInst [ ], INST *iPtr, int address, int
		nwords, FUNCPTR prtAddress);
static int dsmNwords (USHORT binInst [ ], INST *iPtr);
static int fppNwords (USHORT mode, USHORT reg, USHORT rm, USHORT src, USHORT
		extension [ ]);
static int modeNwords (USHORT mode, USHORT reg, int size, USHORT extension [
		]);
static int mode6And7Words (USHORT extension [ ]);
static void prtArgs (USHORT binInst [ ], INST *iPtr, int address, FUNCPTR
		prtAddress);
static void prContReg (USHORT contReg);
static void prEffAddr (USHORT mode, USHORT reg, USHORT extension [ ], int
		size, FUNCPTR prtAddress);
static void prMovemRegs (USHORT extension, USHORT mode);
static void prFmovemr (USHORT mode, USHORT rlist);
static void prFmovemcr (USHORT rlist);
static void prtSizeField (USHORT binInst [ ], INST *iPtr);
static void nPrtAddress (int address);
static void prOffWid (USHORT dO, USHORT offset, USHORT dW, USHORT width);
static void prIndirectIndex (USHORT extension [ ], USHORT mode, USHORT reg);
static void prDisplace (USHORT size, USHORT pDisp [ ]);


/*
This table is ordered by the number of bits in an instruction's
two word mask, beginning with the greatest number of bits in masks.
This scheme is used for avoiding conflicts between instructions
when matching bit patterns.  The instruction ops are arranged
sequentially within each group of instructions for a particular
mask so that uniqueness can be easily spotted.
*/

LOCAL INST inst [] =
    {
    /*   26 bit mask */
    {"DIVU",	itDivL, 0x4c40, 0x0000,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x0800,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x1001,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x1801,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x2002,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x2802,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x3003,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x3803,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x4004,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x4804,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x5005,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x5805,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x6006,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x6806,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVU",	itDivL, 0x4c40, 0x7007,	  0xffc0, 0xffff,    0x02, 0x00},
    {"DIVS",	itDivL, 0x4c40, 0x7807,	  0xffc0, 0xffff,    0x02, 0x00},

    /*   24 bit mask */
    {"ORI",	itImmCCR, 0x003c, 0x0000, 0xffff, 0xff00,    0x00, 0x00},
								    /* to CCR */
    {"ANDI",	itImmCCR, 0x023c, 0x0000, 0xffff, 0xff00,    0x00, 0x00},
								    /* to CCR */
    {"EORI",	itImmCCR, 0x0a3c, 0x0000, 0xffff, 0xff00,    0x00, 0x00},
								   /* to CCR */
    {"CAS2",	itCas2,   0x0cfc, 0x0000, 0xffff, 0x0e38,    0x00, 0x00},
    {"CAS2",	itCas2,   0x0efc, 0x0000, 0xffff, 0x0e38,    0x00, 0x00},

    /*     22 bit mask	*/
    {"CHK2",	itChk2, 0x00c0, 0x0800,	  0xffc0, 0x0fff,    0x9b, 0x10},
    {"CMP2",	itChk2, 0x00c0, 0x0000,	  0xffc0, 0x0fff,    0x9b, 0x10},
    {"CHK2",	itChk2, 0x02c0, 0x0800,   0xffc0, 0x0fff,    0x9b, 0x10},
    {"CMP2",	itChk2, 0x02c0, 0x0000,	  0xffc0, 0x0fff,    0x9b, 0x10},
    {"CHK2",	itChk2, 0x04c0, 0x0800,	  0xffc0, 0x0fff,    0x9b, 0x10},
    {"CMP2",	itChk2, 0x04c0, 0x0000,	  0xffc0, 0x0fff,    0x9b, 0x10},
    {"MOVES",	itMoves,0x0e00, 0x0000,   0xffc0, 0x0fff,    0x83, 0x1c},
    {"MOVES",	itMoves,0x0e40, 0x0000,   0xffc0, 0x0fff,    0x83, 0x1c},
    {"MOVES",	itMoves,0x0e80, 0x0000,   0xffc0, 0x0fff,    0x83, 0x1c},

    /*     21 bit mask	*/
    {"CAS",	itCas, 0x0ac0, 0x0000,	  0xffc0, 0xfe38,    0x83, 0x1c},
    {"CAS",	itCas, 0x0cc0, 0x0000,	  0xffc0, 0xfe38,    0x83, 0x1c},
    {"CAS",	itCas, 0x0ec0, 0x0000,	  0xffc0, 0xfe38,    0x83, 0x1c},

    /*   Fpp instructions */
    {"FABS",	itFabs,   0xf200, 0x0018,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FACOS",   itFacos,  0xf200, 0x001c,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FADD",    itFadd,   0xf200, 0x0022,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FASIN",	itFasin,  0xf200, 0x000c,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FATAN",	itFatan,  0xf200, 0x000a,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FATANH",	itFatanh, 0xf200, 0x000b,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FCMP",	itFcmp,   0xf200, 0x0038,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FCOS",	itFcos,   0xf200, 0x001d,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FCOSH",	itFcosh,  0xf200, 0x0019,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FDB",	itFdb,    0xf248, 0x0000,   0xfff8, 0xffc0,    0x00, 0x00},
    {"FDIV",	itFdiv,   0xf200, 0x0020,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FETOX",	itFetox,  0xf200, 0x0010,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FETOXM1",	itFetoxm1,0xf200, 0x0008,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FGETEXP",	itFgetexp,0xf200, 0x001e,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FGETMAN",	itFgetman,0xf200, 0x001f,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FINT",	itFint,   0xf200, 0x0001,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FINTRZ",	itFintrz, 0xf200, 0x0003,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FLOG10",	itFlog10, 0xf200, 0x0015,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FLOG2",	itFlog2,  0xf200, 0x0016,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FLOGN",	itFlogn,  0xf200, 0x0014,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FLOGNP1",	itFlognp1,0xf200, 0x0006,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FMOD",	itFmod,   0xf200, 0x0021,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FMOVE",	itFmove,  0xf200, 0x0000,   0xffc0, 0xffff,    0x00, 0x00},
    {"FMOVE",	itFmove,  0xf200, 0x4000,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FMOVE",	itFmovek, 0xf200, 0x6000,   0xffc0, 0xe000,    0x82, 0x1c},
    {"FMOVE",	itFmovel, 0xf200, 0x8000,   0xffc0, 0xe3ff,    0x00, 0x00},
    {"FMOVE",	itFmovel, 0xf200, 0xa000,   0xffc0, 0xe3ff,    0x80, 0x1c},
    {"FMOVECR",	itFmovecr,0xf200, 0x5c00,   0xffc0, 0xfc00,    0x00, 0x00},
    {"FMOVEM",	itFmovem, 0xf200, 0xc000,   0xffc0, 0xe700,    0x83, 0x10},
    {"FMOVEM",	itFmovem, 0xf200, 0xe000,   0xffc0, 0xe700,    0x83, 0x1c},
    {"FMOVEM",	itFmovemc,0xf200, 0xc000,   0xffc0, 0xe3ff,    0x00, 0x00},
    {"FMOVEM",	itFmovemc,0xf200, 0xe000,   0xffc0, 0xe3ff,    0x80, 0x1c},
    {"FMUL",	itFmul,   0xf200, 0x0023,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FMUL",	itFmul,   0xf200, 0x4023,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FNEG",	itFneg,   0xf200, 0x001a,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FNEG",	itFneg,   0xf200, 0x401a,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FNOP",	itFnop,   0xf200, 0x0000,   0xffc0, 0xffff,    0x00, 0x00},
    {"FREM",	itFrem,   0xf200, 0x0025,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FREM",	itFrem,   0xf200, 0x4025,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSCALE",	itFscale, 0xf200, 0x0026,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSCALE",	itFscale, 0xf200, 0x4026,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FS",	itFs,     0xf200, 0x0000,   0xffc0, 0xffc0,    0x82, 0x1c},
    {"FSGLDIV",	itFsgldiv,0xf200, 0x0024,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSGLDIV",	itFsgldiv,0xf200, 0x4024,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSGLMUL",	itFsglmul,0xf200, 0x0027,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSGLMUL",	itFsglmul,0xf200, 0x4027,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSIN",	itFsin,   0xf200, 0x000e,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSIN",	itFsin,   0xf200, 0x400e,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSINCOS",	itFsincos,0xf200, 0x0030,   0xffc0, 0xe078,    0x00, 0x00},
    {"FSINCOS",	itFsincos,0xf200, 0x4030,   0xffc0, 0xe078,    0x00, 0x00},
    {"FSINH",	itFsinh,  0xf200, 0x0002,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSINH",	itFsinh,  0xf200, 0x4002,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSQRT",	itFsqrt,  0xf200, 0x0004,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSQRT",	itFsqrt,  0xf200, 0x4004,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FSUB",	itFsub,   0xf200, 0x0028,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSUB",	itFsub,   0xf200, 0x4028,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FTAN",	itFtan,   0xf200, 0x000f,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FTAN",	itFtan,   0xf200, 0x400f,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FTANH",	itFtanh,  0xf200, 0x0009,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FTANH",	itFtanh,  0xf200, 0x4009,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FTENTOX",	itFtentox,0xf200, 0x0012,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FTENTOX",	itFtentox,0xf200, 0x4012,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FTRAP",	itFtrap,  0xf200, 0x0000,   0xffc0, 0xffc0,    0x00, 0x00},
    {"FTST",	itFtst,   0xf200, 0x003a,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FTST",	itFtst,   0xf200, 0x403a,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FTWOTOX",	itFtwotox,0xf200, 0x0011,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FTWOTOX",	itFtwotox,0xf200, 0x4011,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FB",	itFb,     0xf280, 0x0000,   0xff80, 0x0000,    0x00, 0x00},
    {"FRESTORE",itFrestore,0xf340,0x0000,   0xffc0, 0x0000,    0x93, 0x10},
    {"FSAVE",	itFsave,  0xf300, 0x0000,   0xffc0, 0x0000,    0x8b, 0x1c},

#if (CPU==MC68040 || CPU==MC68060 || CPU == MC68LC040)
    {"PFLUSHN",itPflush,  0xf500, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"PFLUSH", itPflush,  0xf508, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"PFLUSHAN",itPflush, 0xf510, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"PFLUSHA",itPflush,  0xf518, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"PTESTW", itPtest,   0xf548, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"PTESTR", itPtest,   0xf568, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},

    {"CINVL",  itCinv,    0xf408, 0x0000, 0xff38, 0x0000,    0x00, 0x00},
    {"CINVP",  itCinv,    0xf410, 0x0000, 0xff38, 0x0000,    0x00, 0x00},
    {"CINVA",  itCinva,   0xf418, 0x0000, 0xff38, 0x0000,    0x00, 0x00},

    {"CPUSHL", itCpush,	  0xf428, 0x0000, 0xff38, 0x0000,    0x00, 0x00},
    {"CPUSHP", itCpush,	  0xf430, 0x0000, 0xff38, 0x0000,    0x00, 0x00},
    {"CPUSHA", itCpusha,  0xf438, 0x0000, 0xff38, 0x0000,    0x00, 0x00},

    {"MOVE16", itMove16,  0xf620, 0x8000, 0xfff8, 0x8fff,    0x00, 0x00},
    {"MOVE16", itMove16L, 0xf600, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"MOVE16", itMove16L, 0xf608, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"MOVE16", itMove16L, 0xf610, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},
    {"MOVE16", itMove16L, 0xf618, 0x0000, 0xfff8, 0x0000,    0x00, 0x00},

    /* 68040 alternations to the 68881/2 instruction set */

    /* XXX bug in Motorola manual */
    /*
    {"FSABS",	itFabs,   0xf200, 0x00??,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FDABS",	itFabs,   0xf200, 0x00??,   0xffc0, 0xa07f,    0x02, 0x00},
    */

    {"FSADD",   itFadd,   0xf200, 0x0062,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FDADD",   itFadd,   0xf200, 0x0066,   0xffc0, 0xa07f,    0x02, 0x00},

    {"FSDIV",   itFdiv,   0xf200, 0x0060,   0xffc0, 0xa07f,    0x02, 0x00},
    {"FDDIV",   itFdiv,   0xf200, 0x0064,   0xffc0, 0xa07f,    0x02, 0x00},

    {"FSMOVE",  itFmove,  0xf200, 0x0040,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FDMOVE",  itFmove,  0xf200, 0x0044,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSMOVE",  itFmove,  0xf200, 0x4040,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FDMOVE",  itFmove,  0xf200, 0x4044,   0xffc0, 0xe07f,    0x02, 0x00},

    {"FSMUL",   itFmul,   0xf200, 0x0063,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FDMUL",   itFmul,   0xf200, 0x0067,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSMUL",   itFmul,   0xf200, 0x4063,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FDMUL",   itFmul,   0xf200, 0x4067,   0xffc0, 0xe07f,    0x02, 0x00},

    {"FSNEG",   itFneg,   0xf200, 0x005a,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FDNEG",   itFneg,   0xf200, 0x005e,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSNEG",   itFneg,   0xf200, 0x405a,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FDNEG",   itFneg,   0xf200, 0x405e,   0xffc0, 0xe07f,    0x02, 0x00},

    {"FSSQRT",  itFsqrt,  0xf200, 0x0041,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FDSQRT",  itFsqrt,  0xf200, 0x0045,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSSQRT",  itFsqrt,  0xf200, 0x4041,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FDSQRT",  itFsqrt,  0xf200, 0x4045,   0xffc0, 0xe07f,    0x02, 0x00},

    {"FSSUB",   itFsub,   0xf200, 0x0068,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FDSUB",   itFsub,   0xf200, 0x006c,   0xffc0, 0xe07f,    0x00, 0x00},
    {"FSSUB",   itFsub,   0xf200, 0x4068,   0xffc0, 0xe07f,    0x02, 0x00},
    {"FDSUB",   itFsub,   0xf200, 0x406c,   0xffc0, 0xe07f,    0x02, 0x00},

#endif	/* (CPU==MC68040) || (CPU == MC68060) || (CPU == MC68LC040)) */

#if (CPU == MC68020 || CPU == MC68030)
/* MMU instructions */

    {"PFLUSHA",	itPflush, 0xf000, 0x2400, 0xffc0, 0xffff,    0x00, 0x00},
    {"PFLUSH",	itPflush, 0xf000, 0x3000, 0xffc0, 0xff1f,    0x00, 0x00},
    {"PMOVEFD",	itPmove,  0xf000, 0x0800, 0xffc0, 0xfdcf,    0x9b, 0x1c},
    {"PMOVE",	itPmove,  0xf000, 0x0900, 0xffc0, 0xfdcf,    0x9b, 0x1c},
    {"PMOVEFD",	itPmove,  0xf000, 0x0c00, 0xffc0, 0xfdcf,    0x9b, 0x1c},
    {"PMOVE",	itPmove,  0xf000, 0x0d00, 0xffc0, 0xfdcf,    0x9b, 0x1c},

    {"PLOADW",	itPload,  0xf000, 0x2000, 0xffc0, 0xffff,    0xc9, 0x1c},
    {"PLOADW",	itPload,  0xf000, 0x2001, 0xffc0, 0xffff,    0xc9, 0x1c},
    {"PLOADW",	itPload,  0xf000, 0x2008, 0xffc0, 0xfff8,    0xc9, 0x1c},
    {"PLOADW",	itPload,  0xf000, 0x2010, 0xffc0, 0xfff8,    0xc9, 0x1c},
    {"PLOADR",	itPload,  0xf000, 0x2200, 0xffc0, 0xffff,    0xc9, 0x1c},
    {"PLOADR",	itPload,  0xf000, 0x2201, 0xffc0, 0xffff,    0xc9, 0x1c},
    {"PLOADR",	itPload,  0xf000, 0x2208, 0xffc0, 0xfff8,    0xc9, 0x1c},
    {"PLOADR",	itPload,  0xf000, 0x2210, 0xffc0, 0xfff8,    0xc9, 0x1c},

    {"PFLUSH",	itPflush, 0xf000, 0x3001, 0xffc0, 0xff1f,    0x00, 0x00},
    {"PFLUSH",	itPflush, 0xf000, 0x3008, 0xffc0, 0xff18,    0x00, 0x00},