dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

    {"LSR",	itMemShift, 0xe2c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},
    {"LSL",	itMemShift, 0xe3c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},
    {"ROXR",	itMemShift, 0xe4c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},
    {"ROXL",	itMemShift, 0xe5c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},
    {"ROR",	itMemShift, 0xe6c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},
    {"ROL",	itMemShift, 0xe7c0, 0x0000,  0xffc0, 0x0000,    0x83, 0x1c},

    /*     10 bit mask	*/
    {"CMPM",	itCmpm, 0xb108, 0x0000,	  0xf1f8, 0x0000,    0x00, 0x00},
    {"CMPM",	itCmpm, 0xb148,	0x0000,   0xf1f8, 0x0000,    0x00, 0x00},
    {"CMPM",	itCmpm, 0xb188, 0x0000,	  0xf1f8, 0x0000,    0x00, 0x00},
    {"EXG",	itExg,  0xc140,	0x0000,   0xf1f8, 0x0000,    0x00, 0x00},
    {"EXG",	itExg,  0xc148,	0x0000,   0xf1f8, 0x0000,    0x00, 0x00},
    {"EXG",	itExg,  0xc188,	0x0000,   0xf1f8, 0x0000,    0x00, 0x00},

    /*     9 bit mask	*/
    {"MOVEM",	itMovem, 0x4880, 0x0000, 0xff80, 0x0000,    0x8b, 0x1c},
    {"MOVEM",	itMovem, 0x4c80, 0x0000, 0xff80, 0x0000,    0x93, 0x10},
    {"SBCD",	itBcd,   0x8100, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"PACK",	itPack,  0x8140, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"UNPK",	itPack,  0x8180, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"ABCD",	itBcd,   0xc100, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"SUBX",	itX,     0x9100, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"SUBX",	itX,     0x9140, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"SUBX",	itX,     0x9180, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"ADDX",	itX,     0xd100, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"ADDX",	itX,     0xd140, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},
    {"ADDX",	itX,     0xd180, 0x0000, 0xf1f0, 0x0000,    0x00, 0x00},


    /*     8 bit mask	*/
    {"NEGX",	itNegx, 0x4000,	0x0000,   0xff00, 0x0000,    0x82, 0x1c},
    {"CLR",	itNegx, 0x4200,	0x0000,   0xff00, 0x0000,    0x82, 0x1c},
    {"NEG",	itNegx, 0x4400,	0x0000,   0xff00, 0x0000,    0x82, 0x1c},
    {"NOT",	itNegx, 0x4600,	0x0000,   0xff00, 0x0000,    0x82, 0x1c},
    {"TST",	itNegx, 0x4a00,	0x0000,   0xff00, 0x0000,    0x80, 0x10},
    {"BRA",	itBra,  0x6000,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BSR",	itBra,  0x6100,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BHI",	itBra,  0x6200, 0x0000,	  0xff00, 0x0000,    0x00, 0x00},
    {"BLS",	itBra,  0x6300,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BCC",	itBra,  0x6400,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BCS",	itBra,  0x6500,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BNE",	itBra,  0x6600,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BEQ",	itBra,  0x6700,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BVC",	itBra,  0x6800,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BVS",	itBra,  0x6900,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BPL",	itBra,  0x6a00,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BMI",	itBra,  0x6b00,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BGE",	itBra,  0x6c00,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BLT",	itBra,  0x6d00, 0x0000,	  0xff00, 0x0000,    0x00, 0x00},
    {"BGT",	itBra,  0x6e00,	0x0000,   0xff00, 0x0000,    0x00, 0x00},
    {"BLE",	itBra,  0x6f00,	0x0000,   0xff00, 0x0000,    0x00, 0x00},

#if defined (MCF52PLUS)
    {"WDDATA",  itNegx, 0xfb00, 0x0000,   0xff00, 0x0000,    0x00, 0x00},
#endif defined (MCF52PLUS)

    /*     7 bit mask	*/
    {"BTST",	itDynBit, 0x0100, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"BCHG",	itDynBit, 0x0140, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"BCLR",	itDynBit, 0x0180, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"BSET",	itDynBit, 0x01c0, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"CHK",	itChk,    0x4100, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"CHK",	itChk,    0x4180, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"LEA",	itLea,    0x41c0, 0x0000,  0xf1c0, 0x0000,    0x9b, 0x10},
    {"DIVU",	itDivW,   0x80c0, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"DIVS",	itDivW,   0x81c0, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"SUB",	itOr,     0x9000, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"SUB",	itOr,     0x9040, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"SUB",	itOr,     0x9080, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"SUBA",	itAdda,   0x90c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"SUB",	itOr,     0x9100, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"SUB",	itOr,     0x9140, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"SUB",	itOr,     0x9180, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"SUBA",	itAdda,   0x91c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"CMP",	itOr,     0xb000, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"CMP",	itOr,     0xb040, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"CMP",	itOr,     0xb080, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"CMPA",	itAdda,   0xb0c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"CMPA",	itAdda,   0xb1c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"MULU",	itDivW,   0xc0c0, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"MULS",	itDivW,   0xc1c0, 0x0000,  0xf1c0, 0x0000,    0x02, 0x00},
    {"ADD",	itOr,     0xd000, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"ADD",	itOr,     0xd040, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"ADD",	itOr,     0xd080, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"ADDA",	itAdda,   0xd0c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},
    {"ADD",	itOr,     0xd100, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"ADD",	itOr,     0xd140, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"ADD",	itOr,     0xd180, 0x0000,  0xf1c0, 0x0000,    0x82, 0x1c},
    {"ADDA",	itAdda,   0xd1c0, 0x0000,  0xf1c0, 0x0000,    0x00, 0x00},

    /*     7 bit mask	*/
    {"ASR",	itRegShift, 0xe000,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"LSR",	itRegShift, 0xe008,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"ROXR",	itRegShift, 0xe010,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"ROR",	itRegShift, 0xe018,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"ASL",	itRegShift, 0xe100,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"LSL",	itRegShift, 0xe108,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"ROXL",	itRegShift, 0xe110,0x0000,   0xf118, 0x0000,    0x00, 0x00},
    {"ROL",	itRegShift, 0xe118,0x0000,   0xf118, 0x0000,    0x00, 0x00},

    /*     7 bit mask	*/
    {"MOVEP",	itMovep, 0x0080, 0x0000,   0xf038, 0x0000,    0x00, 0x00},
#if defined ( INCLUDE_V4 )
    {"MOV3Q",	itMove3q,0xa140, 0x0000,   0xf1c0, 0x0000,    0x80, 0xfc},
#endif

    /*     6 bit mask	*/
    {"cpBcc",	itCpBcc, 0xf080, 0x0000,   0xf180, 0x0000,    0x00, 0x00},
#if defined ( INCLUDE_V4 )
    {"MVS",	itMvs  , 0x7100, 0x0000,   0xf180, 0x0000,    0x80, 0xe0},
    {"MVZ",	itMvz  , 0x7180, 0x0000,   0xf180, 0x0000,    0x80, 0xe0},
#endif

    /*     5 bit mask	*/
    {"MOVEA",	itMoveA, 0x0040, 0x0000,   0xc1c0, 0x0000,    0x00, 0x00},

    /*     5 bit mask	*/
    {"ADDQ",	itQuick, 0x5000, 0x0000,  0xf100, 0x0000,    0x80, 0x1c},
    {"SUBQ",	itQuick, 0x5100, 0x0000,  0xf100, 0x0000,    0x80, 0x1c},
    {"MOVEQ",	itMoveq, 0x7000, 0x0000,  0xf100, 0x0000,    0x00, 0x00},

    /*     4 bit mask	*/
    {"MOVE",	itMoveB, 0x1000, 0x0000,  0xf000, 0x0000,    0x82, 0x1c},
    {"MOVE",	itMoveL, 0x2000, 0x0000,  0xf000, 0x0000,    0x82, 0x1c},
    {"MOVE",	itMoveW, 0x3000, 0x0000,  0xf000, 0x0000,    0x82, 0x1c},
    {"OR",	itOr,    0x8000, 0x0000,  0xf100, 0x0000,    0x02, 0x00},
    {"OR",	itOr,    0x8100, 0x0000,  0xf100, 0x0000,    0x83, 0x1c},
    {"EOR",	itOr,    0xb000, 0x0000,  0xf000, 0x0000,    0x82, 0x1c},
    {"AND",	itOr,    0xc000, 0x0000,  0xf100, 0x0000,    0x02, 0x00},
    {"AND",	itOr,    0xc100, 0x0000,  0xf100, 0x0000,    0x83, 0x1c},
    {"",	0,	 0,	 0,       0,	  0,         0,    0}
    };



/*******************************************************************************
*
* dsmFind - disassemble one instruction
*
* This routine figures out which instruction is pointed to by binInst,
* and returns a pointer to the INST which describes it.
*
* RETURNS: pointer to instruction or NULL if unknown instruction.
*/

LOCAL INST *dsmFind
    (
    USHORT binInst []
    )
    {
    FAST INST *iPtr;
    UINT8 instMode;
    UINT8 instReg;

    /* Look first for MAC instructions */
#if defined (INCLUDE_MAC)
    INST *iPtr_add;
    for (iPtr_add = &inst_add [0] ; iPtr_add->mask1 != 0 ; iPtr_add++)
    {
	if ( ((binInst [0] & iPtr_add->mask1) == iPtr_add->op1)
	     && ((binInst [1] & iPtr_add->mask2) == iPtr_add->op2)
	     )
	{
	    /* get address mode */

	    instMode = (binInst [0] & 0x0038) >> 3;
	    instReg = binInst [0] & 0x0007;

	    /* check effective address mode */

	    if (((1 << instMode ) & iPtr_add->modemask) == 0x00)
	    {
	        return (iPtr_add);
	    }

	    if ((((1 << instMode ) & iPtr_add->modemask) == 0x80) &&
		(((1 << instReg) & iPtr_add->regmask) == 0x00))
	        {
	        return (iPtr_add);
		}

     	}
    }

    /* end of "Look first for MAC instructions"  */
#endif
    
    /* Find out which instruction it is */

    for (iPtr = &inst [0]; iPtr->mask1 != 0; iPtr++)
    {
	if (((binInst [0] & iPtr->mask1) == iPtr->op1)
	     && ((binInst[1] & iPtr->mask2) == iPtr->op2))
	    {
	    /* get address mode */

	    if (strcmp (iPtr->name, "MOVE") == 0)
		{
		instMode = (binInst[0] & 0x01c0) >> 6;
		instReg  = (binInst[0] & 0x0e00) >> 9;
		}
	    else
		{
	        instMode = (binInst[0] & 0x0038) >> 3;
	        instReg = binInst [0] & 0x0007;
		}

	    /* check effective address mode */

	    if (((1 << instMode ) & iPtr->modemask) == 0x00)
		{
	        return (iPtr);
		}
	    if ((((1 << instMode ) & iPtr->modemask) == 0x80) &&
		(((1 << instReg) & iPtr->regmask) == 0x00))
	        {
	        return (iPtr);
		}

	    }
    }

    /* If we're here, we couldn't find it */

    errnoSet (S_dsmLib_UNKNOWN_INSTRUCTION);
    return (NULL);
    }

/*******************************************************************************
*
* dsmPrint - print a disassembled instruction
*
* This routine prints an instruction in disassembled form.  It takes
* as input a pointer to the instruction, a pointer to the INST
* that describes it (as found by dsmFind()), and an address with which to
* prepend the instruction.
*/

LOCAL void dsmPrint
    (
    USHORT binInst [],          /* Pointer to instructin */
    FAST INST *iPtr,            /* Pointer to INST returned by dsmFind */
    int address,                /* Address with which to prepend instructin */
    int nwords,                 /* Instruction length, in words */
    FUNCPTR prtAddress          /* Address printing function */
    )
    {
    FAST int ix;		/* index into binInst */
    FAST int wordsToPrint;	/* # of 5-char areas to reserve for printing
				   of hex version of instruction */
    wordsToPrint = (((nwords - 1) / 5) + 1) * 5;

    /* Print the address and the instruction, in hex */

    printf ("%06x  ", address);
    for (ix = 0; ix < wordsToPrint; ++ix)
	/* print lines in multiples of 5 words */
	{
	if ((ix > 0) && (ix % 5) == 0)		/* print words on next line */
	    printf ("\n        ");
	printf ((ix < nwords) ? "%04x " : "     ", binInst [ix]);
	}

    if (iPtr == NULL)
	{
	printf ("DC.W        0x%04x\n", binInst[0]);
	return;
	}

    /* Print the instruction mnemonic, the size code (.w, or whatever), and
       the arguments */

    printf ("%-6s", iPtr->name);
    prtSizeField (binInst, iPtr);
    printf ("    ");
    prtArgs (binInst, iPtr, address, prtAddress);
    }
/*******************************************************************************
*
* dsmNwords - return the length (in words) of an instruction
*/

LOCAL int dsmNwords
    (
    USHORT binInst [],
    FAST INST *iPtr
    )
    {
    int frstArg;	/* length of first argument */

    if (iPtr == NULL)
	return (1);			/* not an instruction */

    switch (iPtr->type)
	{
	case itMoveFACC:
	case itMoveFMACSR:
	case itMoveFMASK:
	case itMoveTCCR:
		return (1);

	case itMoveTMASK:
	case itMoveTACC:
	case itMoveTMACSR:
		return (1 + modeNwords((binInst [0] & 0x0038) >> 3  
					,binInst [0] & 7
					, 2,  &binInst [1]
					)
			);
	case itMac:
	case itMsac:
		return (2);

   	 
	case itMacl:
	case itMsacl:
		return (2 + modeNwords((binInst [0] & 0x0038) >> 3  
					,binInst [0] & 7
					, 0,  &binInst [2]
					)
			);
	case itLea:
	case itBcd:
	case itNbcd:
	case itDynBit:
	case itMemShift:
	case itMoveTSR:
	case itMoveFSR:
	case itMoveCCR:
	case itQuick:
	case itScc:
	case itMoveFCCR:
	case itDivW:
	case itCpSave:
	    return (1 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7, 1, &binInst [1]));

	case itMoves:
	case itStatBit:
	case itMovem:
	case itCallm:
	case itBfchg:
	case itBfext:
	case itBfins:
	case itCpGen:
	case itCpScc:
	    return (2 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7, 0, &binInst [2]));

	case itDivL:
	    return (2 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7, 2, &binInst [2]));

	case itAdda:
	    return (1 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x0100) == 0) ? 1 : 2,
				    &binInst [1]));
	case itMoveA:
	    return (1 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x1000) == 0) ? 2 : 1,
				    &binInst [1]));
	case itNegx:
	case itOr:
	    return (1 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x0080) == 0) ? 1 : 2,
				    &binInst [1]));
	case itChk:
	    return (1 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x0080) == 0) ? 2 : 1,
				    &binInst [1]));

	case itChk2:
	    return (2 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x0400) == 0) ? 1 : 2,
				    &binInst [2]));

	case itCas:
	    return (2 + modeNwords ((binInst [0] & 0x0038) >> 3,
				    binInst [0] & 7,
				    ((binInst [0] & 0x0600) == 3) ? 2 : 1,
				    &binInst [2]));

	case itComplete:
	case itMoveq:
	case itExg:
	case itSwap:
	case itTrap:
	case itX:
	case itMoveUSP:
	case itUnlk:
	case itCmpm:
	case itExt:
	case itBkpt:
	case itRtm:
	case itRegShift:
	case itCpush:
	case itIntouch:
	    return (1);

	case itMovep:
	case itStop: