mmualib.s

VxWorks BSP框架源代码包含头文件和驱动

	BIC	r0, r0, #(MMUCR_M_ENABLE | MMUCR_C_ENABLE | MMUCR_W_ENABLE)
	MCR	CP_MMU, 0, r0, c1, c0, 0	/* Write the control register */
#else
	BIC	r0, r0, #(MMUCR_M_ENABLE | MMUCR_C_ENABLE | MMUCR_W_ENABLE)
	MCR	CP_MMU, 0, r0,c1, c0, 0		/* Write the control register */
#endif /* BPRED_SUPPORT */
#endif /* (ARMMMU == ARMMMU_810) */

#if ARMMMU_1020E_REV0_MCR_CP15
        NOP
        NOP
#endif

	/*
	 * On StrongARM, the next three instructions will be fetched
	 * "translated".* On 710A and 810, the next two instructions will
	 * be fetched "translated". On ARM ( CPUs this can be three
	 * instructions.  If this code is called from a piece
	 * of code in an area whose virtual address will not be the same
	 * as its physical address, problems will ensue. However, it is
	 * not clear what steps we can take to protect against this
	 * here.
	 */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#if (ARM_HAS_MPU)
/*******************************************************************************
*
* mmuPrrSet - write the Protection Region Register(s) (ARM)
*
* This routine writes to the Data and Instruction Protection Region Registers
* (just one combined I-D register on 740T).
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuPrrSet
*	(
*	const UINT32 *	pPegs	/@ pointer to array of register values @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuPrrSet)

	/* Set registers(s) with value from R0 */

#if (ARM_THUMB)
	STMFD	sp!, {r4-r7}			/* Save registers */
#else
	STMFD	sp!, {r4-r7, lr}		/* Save registers */
#endif
	MOV	ip, r0				/* get pointer to block */
	LDMIA	ip, {r0-r7}			/* read from block of memory */
#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_946E))
	MCR	CP_MMU, 0, r0, c6, c0, 0	/* write registers in MMU */
	MCR	CP_MMU, 0, r0, c6, c0, 1	/* for Instruction and Data */
	MCR	CP_MMU, 0, r1, c6, c1, 0	/* for all 8 regions */
	MCR	CP_MMU, 0, r1, c6, c1, 1	/* Make I and D descriptions */
	MCR	CP_MMU, 0, r2, c6, c2, 0	/* identical */
	MCR	CP_MMU, 0, r2, c6, c2, 1
	MCR	CP_MMU, 0, r3, c6, c3, 0
	MCR	CP_MMU, 0, r3, c6, c3, 1
	MCR	CP_MMU, 0, r4, c6, c4, 0
	MCR	CP_MMU, 0, r4, c6, c4, 1
	MCR	CP_MMU, 0, r5, c6, c5, 0
	MCR	CP_MMU, 0, r5, c6, c5, 1
	MCR	CP_MMU, 0, r6, c6, c6, 0
	MCR	CP_MMU, 0, r6, c6, c6, 1
	MCR	CP_MMU, 0, r7, c6, c7, 0
	MCR	CP_MMU, 0, r7, c6, c7, 1
#endif /* (ARMMMU == ARMMMU_940T,946E) */
#if (ARMMMU == ARMMMU_740T)
	MCR	CP_MMU, 0, r0, c6, c0, 0	/* write registers in MMU */
	MCR	CP_MMU, 0, r1, c6, c1, 0	/* for all 8 regions */
	MCR	CP_MMU, 0, r2, c6, c2, 0
	MCR	CP_MMU, 0, r3, c6, c3, 0
	MCR	CP_MMU, 0, r4, c6, c4, 0
	MCR	CP_MMU, 0, r5, c6, c5, 0
	MCR	CP_MMU, 0, r6, c6, c6, 0
	MCR	CP_MMU, 0, r7, c6, c7, 0
#endif /* (ARMMMU == ARMMMU_740T) */
#if (ARM_THUMB)
	LDMFD	sp!, {r4-r7}			/* restore registers and exit */
	BX	lr
#else
	LDMFD	sp!, {r4-r7, pc}		/* restore registers and exit */
#endif

/*******************************************************************************
*
* mmuPrrGet - read the Protection Region Register(s) (ARM)
*
* This routine reads the Data Space Protection Region Registers
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuPrrGet
*	(
*	UINT32 *	pPegs	/@ pointer to array of register values @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuPrrGet)
#if (ARM_THUMB)
	STMFD	sp!, {r4-r7}			/* Save registers */
#else
	STMFD	sp!, {r4-r7, lr}		/* Save registers */
#endif
	MOV	ip, r0				/* get pointer to block */
	MRC	CP_MMU, 0, r0, c6, c0, 0	/* read registers from MMU */
	MRC	CP_MMU, 0, r1, c6, c1, 0	/* for all 8 regions */
	MRC	CP_MMU, 0, r2, c6, c2, 0
	MRC	CP_MMU, 0, r3, c6, c3, 0
	MRC	CP_MMU, 0, r4, c6, c4, 0
	MRC	CP_MMU, 0, r5, c6, c5, 0
	MRC	CP_MMU, 0, r6, c6, c6, 0
	MRC	CP_MMU, 0, r7, c6, c7, 0
	STMIA	ip, {r0-r7}			/* store to block of memory */
#if (ARM_THUMB)
	LDMFD	sp!, {r4-r7}			/* restore registers and exit */
	BX	lr
#else
	LDMFD	sp!, {r4-r7, pc}		/* restore registers and exit */
#endif

/*******************************************************************************
*
* mmuCcrSet - write the Cache Control Registers (ARM)
*
* This routine writes to the Cache Control Registers
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuCcrSet
*	(
*	UINT32	val	/@ value to write to registers @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuCcrSet)

	MCR	CP_MMU, 0, r0, c2, c0, 0	/* Set reg with val from R0 */
#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_946E))
	MCR	CP_MMU, 0, r0, c2, c0, 1	/* Set reg with val from R0 */
#endif /* (ARMMMU == ARMMMU_940T,946E) */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuCcrGet - read the Cache Control Register (ARM)
*
* This routine reads the Instruction Cache Control Register
*
* RETURNS: the value read
*
* NOMANUAL
*
* UINT32 mmuCcrGet (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuCcrGet)

	MRC	CP_MMU, 0, r0, c2, c0, 0	/* Read val into R0 */
#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuWbcrSet - write the Write Buffer Control Register (ARM)
*
* This routine writes to the Write Buffer Control Register
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuWbcrSet
*	(
*	UINT32	val	/@ value to write to register @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuWbcrSet)

	MCR	CP_MMU, 0, r0, c3, c0, 0	/* Set reg with val from R0 */
#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuWbcrGet - read the Write Buffer Control Register (ARM)
*
* This routine reads the Write Buffer Control Register
*
* RETURNS: the value read
*
* NOMANUAL
*
* UINT32 mmuWbcrGet (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuWbcrGet)

	MRC	CP_MMU, 0, r0, c3, c0, 0	/* Read val into R0 */
#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuPrSet - write the Protection Registers (ARM)
*
* This routine writes to the Protection Registers
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuPrSet
*	(
*	UINT32	val	/@ value to write to register @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuPrSet)

	MCR	CP_MMU, 0, r0, c5, c0, 0	/* Set reg with val from R0 */
#if ((ARMMMU == ARMMMU_940T) || (ARMMMU == ARMMMU_946E))
	MCR	CP_MMU, 0, r0, c5, c0, 1	/* Set reg with val from R0 */
#endif /*(ARMMMU == ARMMMU_940T,946E) */
#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuPrGet - read the Protection Register (ARM)
*
* This routine reads the Instruction space Protection Register
*
* RETURNS: the value read
*
* NOMANUAL
*
* UINT32 mmuPrGet (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuPrGet)

	MRC	CP_MMU, 0, r0, c5, c0, 0	/* Read val into R0 */
#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#endif /* (ARM_HAS_MPU) */

#if (!ARM_HAS_MPU)
/*******************************************************************************
*
* mmuTLBIDFlushEntry - flush an entry in both I and D TLBs (ARM)
*
* This routine flushes (invalidates) an entry in the instruction and data
* TLBs.
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuTLBIDFlushEntry
*	(
*	void *	addr	/@ (virtual) address of entry to flush @/
*	)
*
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuTLBIDFlushEntry)

#if (ARMMMU == ARMMMU_710A)
	MCR	CP_MMU, 0, r0, c6, c0, 0	/* Flush ID TLB entry */
#endif

#if ((ARMMMU == ARMMMU_810) || (ARMMMU == ARMMMU_720T))
	MCR	CP_MMU, 0, r0, c8, c7, 1	/* Flush ID TLB entry */
#endif

#if ((ARMMMU == ARMMMU_SA110)  || \
     (ARMMMU == ARMMMU_SA1100) || (ARMMMU == ARMMMU_SA1500))
	/* Cannot flush I TLB entry, only all of it */

	MCR	CP_MMU, 0, r0, c8, c5, 0	/* Flush all I TLB */

	MCR	CP_MMU, 0, r0, c8, c6, 1	/* Flush D TLB entry */
#endif

#if ((ARMMMU == ARMMMU_920T)   || (ARMMMU == ARMMMU_XSCALE) || \
     (ARMMMU == ARMMMU_1020E)  || (ARMMMU == ARMMMU_1022E))
	/*
	 * bits [0:9] of VA SBZ, and should be so, as we are called via
	 * vmLib, which will ensure that the address is page-aligned.
	 */

	MCR	CP_MMU, 0, r0, c8, c5, 1	/* Flush I TLB entry */
	MCR	CP_MMU, 0, r0, c8, c6, 1	/* Flush D TLB entry */

#if (ARMMMU == ARMMMU_XSCALE)
	/* assure that CP15 update takes effect */

	MRC	CP_MMU, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
	MOV	r0, r0			 /* wait for it */
	SUB	pc, pc, #4		 /* branch to next instruction */
#endif
#if ARMMMU_1020E_REV0_MCR_CP15
        NOP
        NOP
#endif
#endif /* (ARMMMU == ARMMMU_920T,XSCALE,1020E,1022E) */

#if (ARMMMU == ARMMMU_926E)
        /*
         * On ARM926ES-J, there is a co-proc op to invalidate any TLB entries
         * for a particular address, whichever TLB it is in.
         */
        MCR     CP_MMU, 0, r0, c8, c7, 1        /* Flush I and D TLB entries */
#endif

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

/*******************************************************************************
*
* mmuTLBIDFlushAll - flush all entries in both I and D TLBs (ARM)
*
* This routine flushes (invalidates) all entries in the instruction and data
* TLBs.
*
* RETURNS: N/A
*
* NOMANUAL
*
* void mmuTLBIDFlushAll (void)
*
*/

_ARM_FUNCTION_CALLED_FROM_C(mmuTLBIDFlushAll)

#if (ARMMMU == ARMMMU_710A)
	MCR	CP_MMU, 0, r0, c5, c0, 0	/* Flush all of TLB */
#endif

#if ((ARMMMU == ARMMMU_720T)   || (ARMMMU == ARMMMU_810)    || \
     (ARMMMU == ARMMMU_SA110)  || (ARMMMU == ARMMMU_SA1100) || \
     (ARMMMU == ARMMMU_SA1500) || (ARMMMU == ARMMMU_920T)   || \
     (ARMMMU == ARMMMU_926E)   || (ARMMMU == ARMMMU_XSCALE) || \
     (ARMMMU == ARMMMU_1020E)  || (ARMMMU == ARMMMU_1022E))

#if ((ARMMMU == ARMMMU_720T)   || (ARMMMU == ARMMMU_810)    || \
     (ARMMMU == ARMMMU_920T)   || (ARMMMU == ARMMMU_926E)   || \
     (ARMMMU == ARMMMU_XSCALE) || (ARMMMU == ARMMMU_1020E)  || \
     (ARMMMU == ARMMMU_1022E))
	MOV	r0, #0				/* datasheet says data SBZ */
#endif

	MCR	CP_MMU, 0, r0, c8, c7, 0	/* Flush all I+D TLBs */
#endif

#if (ARMMMU == ARMMMU_XSCALE)
	/* assure that CP15 update takes effect */

	MRC	CP_MMU, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
	MOV	r0, r0			 /* wait for it */
	SUB	pc, pc, #4		 /* branch to next instruction */
#endif

#if ARMMMU_1020E_REV0_MCR_CP15
        NOP
        NOP
#endif

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#endif /* (!ARM_HAS_MPU) */

#endif /* ARMMMU == 710A,720T,740T,810,SA*,920T,926E,940T,946E,XSCALE,1020E,1022E */