cachealib.s

VxWorks BSP框架源代码包含头文件和驱动

	LDR	r1, L$_cacheArchIndexMask /* Get ptr to num of lines - 1 */
	LDR	r1, [r1]		/* number of indices to clean */
5:
	MOV	r2, #(3<<30)		/* 4 segments */
6:
	ORR	r0, r2, r1		/* Create Index, Seg format */
	MCR	CP_MMU, 0, r0, c7, c10, 2 /* Clean D-cache entry */
	SUBS	r2, r2, #(1<<30)	/* step on to next segment */
	BHS	6b			/* branch if not done all segs */
	SUBS	r1, r1, #(1<<5)		/* step on to next index */
	BHS	5b			/* branch if not done all indices */
					/* All Index, Seg entries cleaned */
#endif /* (ARMCACHE == ARMCACHE_946E) */

#if (ARMCACHE == ARMCACHE_920T)
	MOV	r1, #63			/* 64 indices to clean */
5:
	MOV	r2, #(7<<5)		/* 8 segments */
6:
	ORR	r0, r2, r1, LSL #26	/* Create Index, Seg format */
	MCR	CP_MMU, 0, r0, c7, c10, 2 /* Clean D-cache entry */
	SUBS	r2, r2, #(1<<5)		/* step on to next segment */
	BPL	6b			/* branch if not done all segs */
	SUBS	r1, r1, #1		/* step on to next index */
	BPL	5b			/* branch if not done all indices */
					/* All Index, Seg entries cleaned */
	/* Ensure victim pointer does not point to locked entries */

	MRC	CP_MMU, 0, r0, c9, c0, 0  /* Read D-cache lockdown base */
	MCR	CP_MMU, 0, r0, c9, c0, 0  /* Write D-cache lockdown base */
#endif /* (ARMCACHE == ARMCACHE_920T) */

#if (ARMCACHE == ARMCACHE_926E)
5:
        MRC     CP_MMU, 0, pc, c7, c10, 3  /* test, & clean */
        BNE     5b                      /* branch if dirty */
#endif /* (ARMCACHE == ARMCACHE_926E) */

#if (ARMCACHE == ARMCACHE_1020E) || (ARMCACHE == ARMCACHE_1022E)
#if ARMCACHE_1020E_REV0_DRAIN_WB        /* Rev 0 errata */
        MOV     r0, #0                  /* Data SBZ */
        MCR     CP_MMU, 0, r0, c7, c10, 4 /* Drain write-buffer */
#endif /* ARMCACHE_1020E_REV0_DRAIN_WB */
        LDR     r1, L$_cacheArchIndexMask /* Get ptr to index mask */
        LDR     r3, L$_cacheArchSegMask /* Get pointer to segment mask */
        LDR     r1, [r1]                /* num indices to clean - 1 shifted */
        LDR     r3, [r3]                /* get num segs to clean -1 shifted */
5:
        MOV     r2, r3                  /* max num segments */
6:
        ORR     r0, r2, r1              /* Create Index, Seg format */
        MCR     CP_MMU, 0, r0, c7, c10, 2 /* Clean D-cache entry */

#if ARMCACHE_1020E_REV0_MCR_CP15
        NOP
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */

        SUBS    r2, r2, #(1<<5)         /* step on to next segment */
        BHS     6b                      /* branch if not done all segs */
        SUBS    r1, r1, #(1<<26)        /* step on to next index */
        BHS     5b                      /* branch if not done all indices */
                                        /* All Index, Seg entries cleaned */
#endif /* (ARMCACHE == ARMCACHE_1020E,1022E) */

#if (ARMCACHE == ARMCACHE_810)
	LDR	r0, L$_cacheSwapVar	/* R0 -> FUNC(_cacheSwapVar) */
	SWPB	r1, r1, [r0]		/* Drain write-buffer */
#endif

#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \
     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \
     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_946E)   || \
     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \
     (ARMCACHE == ARMCACHE_1022E))

#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
     	MOV	r0, #0			    /* data SBZ */
#endif
	MCR	CP_MMU, 0, r0, c7, c10, 4   /* Drain write-buffer */
#if ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15)
        NOP
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */
#endif

#if (ARMCACHE == ARMCACHE_940T)
	LDR	r0, L$_sysCacheUncachedAdrs
	LDR	r0, [r0]		/* R0 -> uncached area */
	LDR	r0, [r0]		/* Drain write-buffer */
#endif /* ARMCACHE == ARMCACHE_940T */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#endif /* (ARMCACHE == ARMCACHE_810,SA*,920T,926E,940T,946E,XSCALE,1020E,1022E) */

/*******************************************************************************
*
* cacheDInvalidateAll - invalidate D-cache (ARM)
*
* This routine invalidates all the Data Cache. On 710A/810/740T/720T this is
* the ID-cache.
*
* NOMANUAL
*
* RETURNS: N/A
*
* void cacheDInvalidateAll (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(cacheDInvalidateAll)

#if ((ARMCACHE == ARMCACHE_710A) || (ARMCACHE == ARMCACHE_740T))
	MCR	CP_MMU, 0, r0, c7, c0, 0 /* Flush (invalidate) all ID-cache */
					/* next two instructions could still */
	NOP				/* come from cache */
#endif/* (710A, 740T) */

#if ((ARMCACHE == ARMCACHE_810) || (ARMCACHE == ARMCACHE_720T))
	MOV	r0, #0			 /* Data SBZ */
	MCR	CP_MMU, 0, r0, c7, c7, 0 /* Flush (invalidate) all ID-cache */
	NOP
#endif

#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \
     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \
     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \
     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))

#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E)   || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
	MOV	r0, #0			/* Data SBZ */
#endif
	MCR	CP_MMU, 0, r0, c7, c6, 0 /* Flush (invalidate) all D-cache */
#if ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15)
        NOP
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */
#endif

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif


#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \
     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \
     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_946E)   || \
     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \
     (ARMCACHE == ARMCACHE_1022E))
/*
 * Not needed on 710A, 720T, 740T, as DInvalidateAll() used instead.
 * Not needed on 810, 940T as DClear used instead.
 */
/*******************************************************************************
*
* cacheDInvalidate - invalidate D-cache entry (ARM)
*
* This routine invalidates an entry in the Data Cache
*
* NOMANUAL
*
* RETURNS: N/A
*
* void cacheDInvalidate
*     (
*     void *	addr	/@ virtual address to be invalidated @/
*     )
*/

_ARM_FUNCTION_CALLED_FROM_C(cacheDInvalidate)

	MCR	CP_MMU, 0, r0, c7, c6, 1 /* Flush (invalidate) D-cache entry */
#if ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15)
        NOP
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#endif

#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \
     (ARMCACHE == ARMCACHE_920T)   || \
     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \
     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
/*******************************************************************************
*
* cacheIInvalidateAll - invalidate I-cache (ARM)
*
* This routine invalidates the Instruction Cache. On return, the I-cache will
* only still be empty if this routine is called with the I-cache off.
*
* NOMANUAL
*
* RETURNS: N/A
*
* void cacheIInvalidateAll (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(cacheIInvalidateAll)

#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E)   || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
	MOV	r0, #0			/* Data SBZ */
#endif
#if ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15)
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */
	MCR	CP_MMU, 0, r0, c7, c5, 0 /* Flush (invalidate) I-cache */

#if (ARMCACHE == ARMCACHE_XSCALE)
        /* assure that CP15 update takes effect */
        MRC     CP_MMU, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
        MOV     r0, r0                   /* wait for it */
        SUB     pc, pc, #4               /* branch to next instruction */
#else
	/*
	 * The next four instructions could still come from the I-cache
	 * (2 on the 940T, 3 on 920T). We also need to flush
	 * the prefetch unit, which will be done by the MOV pc, lr below.
	 */

#if ((ARMCACHE == ARMCACHE_SA110)  || \
     (ARMCACHE == ARMCACHE_SA1100) || (ARMCACHE == ARMCACHE_SA1500))
        NOP                             /* 4 */
        NOP                             /* 3 */
#endif
#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
        NOP                             /* 3 */
#endif
	NOP				/* 2 */
#endif

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr			/* 1 */
#endif
#endif /* ARMCACHE == SA110,1100,1500,920T,940T,926E,946E,XSCALE,1020E */

#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E)   || \
     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \
     (ARMCACHE == ARMCACHE_1022E))
/*******************************************************************************
*
* cacheIInvalidate - invalidate I-cache entry (ARM)
*
* This routine invalidates an entry in the Instruction Cache.
*
* NOMANUAL
*
* RETURNS: N/A
*
* void cacheIInvalidate
*	(
*	void *	addr	/@ virtual address to be invalidated @/
*	)
*/

_ARM_FUNCTION_CALLED_FROM_C(cacheIInvalidate)

#if (ARMCACHE == ARMCACHE_940T)
	LDR	r2, L$_cacheArchIntMask	/* Get pointer to cacheArchIntMask */
	LDR	r2, [r2]		/* get cacheArchIntMask */
	MRS	r3, cpsr		/* Get CPSR */
	ORR	r2, r3, r2		/* disable interrupts */
	MSR	cpsr, r2

	AND	r0, r0, #0x30		/* r0 now contains segment number */
					/* in which addr will be cached */
	MOV	r1, #63			/* 64 indices to clean */
1:
	ORR	r2, r0, r1, LSL #26	/* Create Index, Seg format */
	MCR	CP_MMU, 0, r2, c7, c5, 1 /* Invalidate I-cache entry */
	SUBS	r1, r1, #1		/* step on to next index */
	BPL	1b			/* branch if not done all indices */

	MSR	cpsr, r3		/* Restore interrupt state */
#endif /* (ARMCACHE == ARMCACHE_940T) */


#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \
     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \
     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))
	/* Bits [0:4] of VA SBZ but will be, (called from cacheArchInvalidate)*/

	MCR	CP_MMU, 0, r0, c7, c5, 1 /* Invalidate I-cache entry */
#if ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15)
        NOP
        NOP
#endif /* ((ARMCACHE == ARMCACHE_1020E) && ARMCACHE_1020E_REV0_MCR_CP15) */
#if (ARMCACHE == ARMCACHE_XSCALE)
        /* assure that CP15 update takes effect */

        MRC     CP_MMU, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
        MOV     r0, r0                   /* wait for it */
        SUB     pc, pc, #4               /* branch to next instruction */
#endif

#endif /* (ARMCACHE == ARMCACHE_920T,926E,946E,XSCALE,1020E,1022E) */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif

#endif /* ARMCACHE == ARMCACHE_920T,940T,946E,XSCALE */

#if (ARMCACHE == ARMCACHE_XSCALE)
/*******************************************************************************
*
* btbInvalidate - invalidate Branch Target Buffer (ARM)
*
* This routine invalidates the Branch Target Buffer.
*
* NOTE: If software invalidates a line from the instruction cache and modifies
*       the same location in external memory, it needs to invalidate the BTB.
*
* NOMANUAL
*
* RETURNS: N/A
*
* void btbInvalidate
* (
* void
* )
*/

_ARM_FUNCTION_CALLED_FROM_C(btbInvalidate)

	MCR	CP_MMU, 0, r0, c7, c5, 6 /* Invalidate BTB entry */

	/* assure that CP15 update takes effect */

	MRC	CP_MMU, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
	MOV	r0, r0			/* wait for it */
	SUB	pc, pc, #4		/* branch to next instruction */

#if (ARM_THUMB)
	BX	lr
#else
	MOV	pc, lr
#endif
#endif /* ARMCACHE == XSCALE */

/*******************************************************************************
*
* cacheDClearAll - clear all D-cache and drain Write Buffer (ARM)
*
* This routine clears (flushes and invalidates) all the Data Cache, and
* drains the write-buffer.
*
* NOMANUAL
*
* RETURNS: N/A
*
* void cacheDClearAll (void)
*/

_ARM_FUNCTION_CALLED_FROM_C(cacheDClearAll)

#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \
     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_XSCALE))
	LDR	r0, L$_sysCacheFlushReadArea
	ADD	r1, r0, #D_CACHE_SIZE	/* End of buffer to read */

	LDR	r2, L$_cacheArchIntMask	/* Get pointer to cacheArchIntMask */
	LDR	r2, [r2]		/* get cacheArchIntMask */
	MRS	r3, cpsr		/* Get CPSR */