dbgstrlib.c

VxWorks BSP框架源代码包含头文件和驱动

BOOL dbgStrPebsEnable
    (
    BOOL enable		/* TRUE to enable, FALSE to disable the PEBS */
    )
    {
    int value[2];	/* MSR 64 bits value */
    int oldValue;	/* old value */

    /* check if the PEBS initialization succeeded */

    if (!dbgStrCfg.pebsAvailable)
	return (FALSE);

    /* get the MSR_IQ_CCCR4 value */

    pentiumMsrGet (MSR_IQ_CCCR4, (LL_INT *)&value);
    oldValue = value[0];

    /* enable or disable the PEBS */

    if (enable)
        value[0] |= CCCR_ENABLE;
    else
        value[0] &= ~CCCR_ENABLE;

    /* set the MSR_IQ_CCCR4 value */

    pentiumMsrSet (MSR_IQ_CCCR4, (LL_INT *)&value);

    return ((oldValue & CCCR_ENABLE) ? TRUE : FALSE);
    }

/*******************************************************************************
*
* dbgStrCreateHook - create hook routine for the Debug Store
*
* This routine is the create hook routine for the Debug Store 
*
* RETURNS: N/A
*/

LOCAL void dbgStrCreateHook
    (
    WIND_TCB * pNewTcb		/* pointer to new task's TCB */
    )
    {
    X86_EXT * pExt;		/* X86 TCB extension */
    DS_CONFIG * pC;		/* DS config */

    /* allocate the X86 TCB extension if it is not yet allocated */

    if ((pExt = (X86_EXT *)pNewTcb->reserved2) == 0)
        {
        pExt = (X86_EXT *) taskStackAllot ((int) pNewTcb, sizeof (X86_EXT));
        if (pExt == NULL)
	    return;
    
	bzero ((char *) pExt, sizeof (X86_EXT));
        pNewTcb->reserved2 = (int)pExt;
        }

    /* allocate the DS configuration, and save it in the TCB */

    pC = (DS_CONFIG *) KMEM_ALIGNED_ALLOC (sizeof (DS_CONFIG), 
					   _CACHE_ALIGN_SIZE);
    if (pC == NULL)
	return;
    
    pExt->reserved0 = (UINT32)pC;

    /* inherit the system DS configuration */

    bcopy ((char *)&dbgStrCfg, (char *)pC, sizeof (DS_CONFIG));

    /* allocate and initialize the DS header, BTS/PEBS buffer */

    if (dbgStrBufAlloc (pNewTcb) != OK)
	return;
    }

/*******************************************************************************
*
* dbgStrSwitchHook - switch hook routine for the Debug Store
*
* This routine is the switch hook routine for the Debug Store 
*
* RETURNS: N/A
*/

LOCAL void dbgStrSwitchHook
    (
    WIND_TCB * pOldTcb,	/* pointer to old task's WIND_TCB */
    WIND_TCB * pNewTcb	/* pointer to new task's WIND_TCB */
    )
    {

    /* start/stop the BTS/PEBS with the parameters set by dbgStrConfig() */

    dbgStrStart (pNewTcb);
    }

/*******************************************************************************
*
* dbgStrDeleteHook - delete hook routine for the Debug Store
*
* This routine is the delete hook routine for the Debug Store 
*
* RETURNS: N/A
*/

LOCAL void dbgStrDeleteHook
    (
    WIND_TCB * pTcb	/* pointer to deleted task's WIND_TCB */
    )
    {
    X86_EXT * pExt = NULL;	/* X86 TCB extension */
    DS_CONFIG * pC = NULL;	/* DS config */

    /* if it is current task, stop DS. Otherwise let the switch hook stop */

    if (pTcb == taskIdCurrent)
	{
	dbgStrBtsEnable (FALSE);
	dbgStrPebsEnable (FALSE);
	}

    /* delete the DS header */

    dbgStrBufFree (pTcb);

    /* delete the DS config */

    pExt = (X86_EXT *)pTcb->reserved2;
    if (pExt != NULL)
	pC = (DS_CONFIG *)pExt->reserved0;

    if (pC != NULL)
        KMEM_FREE ((char *)pC);
    }

/*******************************************************************************
*
* dbgStrPebsFrontEnd - set up the PEBS for the Front End event
*
* This routine sets up the PEBS for the Front End event.
*
* RETURNS: OK, or ERROR if the specified metric is not supported.
*/

LOCAL STATUS dbgStrPebsFrontEnd 
    (
    INT32 metric,	/* metric in the event */
    BOOL os		/* TRUE if OS mode, otherwise USR mode */
    )
    {
    int value[2];	/* MSR 64 bits value */

    /* validation check for the metric */

    switch (metric)
	{
	case PEBS_MEMORY_LOADS:

	    value[0] = ESCR_MEMORY_LOADS | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_RAT_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_MEMORY_STORES:

	    value[0] = ESCR_MEMORY_STORES | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_RAT_ESCR0, (LL_INT *)&value);

	    break;

	default:
	    return (ERROR);
	}

    value[0] = ESCR_FRONT_END | (os ? ESCR_OS : ESCR_USR);
    value[1] = 0;
    pentiumMsrSet (MSR_CRU_ESCR2, (LL_INT *)&value);

    value[0] = CCCR_FRONT_END;
    value[1] = 0;
    pentiumMsrSet (MSR_IQ_CCCR4, (LL_INT *)&value);

    value[0] = DS_BIT_25;
    value[1] = 0;
    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

    return (OK);
    }

/*******************************************************************************
*
* dbgStrPebsExec - set up the PEBS for the Execution event
*
* This routine sets up the PEBS for the Execution event.
*
* RETURNS: OK, or ERROR if the specified metric is not supported.
*/

LOCAL STATUS dbgStrPebsExec 
    (
    INT32 metric,	/* metric in the event */
    BOOL os		/* TRUE if OS mode, otherwise USR mode */
    )
    {
    int value[2];	/* MSR 64 bits value */

    /* validation check for the metric */

    switch (metric)
	{
	case PEBS_PACKED_SP:

	    value[0] = ESCR_PACKED_SP | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_PACKED_DP:

	    value[0] = ESCR_PACKED_DP | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_SCALAR_SP:

	    value[0] = ESCR_SCALAR_SP | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_SCALAR_DP:

	    value[0] = ESCR_SCALAR_DP | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_128BIT_MMX:

	    value[0] = ESCR_128BIT_MMX | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_64BIT_MMX:

	    value[0] = ESCR_64BIT_MMX | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_X87_FP:

	    value[0] = ESCR_X87_FP | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_X87_SIMD_MOVES:

	    value[0] = ESCR_X87_SIMD_MOVES | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_FIRM_ESCR0, (LL_INT *)&value);

	    break;

	default:
	    return (ERROR);
	}

    value[0] = ESCR_EXECUTION | (os ? ESCR_OS : ESCR_USR);
    value[1] = 0;
    pentiumMsrSet (MSR_CRU_ESCR2, (LL_INT *)&value);

    value[0] = CCCR_EXECUTION;
    value[1] = 0;
    pentiumMsrSet (MSR_IQ_CCCR4, (LL_INT *)&value);

    value[0] = DS_BIT_25;
    value[1] = 0;
    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

    return (OK);
    }

/*******************************************************************************
*
* dbgStrPebsReplay - set up the PEBS for the Replay event
*
* This routine sets up the PEBS for the Replay event.
*
* RETURNS: OK, or ERROR if the specified metric is not supported.
*/

LOCAL STATUS dbgStrPebsReplay 
    (
    INT32 metric,	/* metric in the event */
    BOOL os		/* TRUE if OS mode, otherwise USR mode */
    )
    {
    int value[2];	/* MSR 64 bits value */

    /* validation check for the metric */

    switch (metric)
	{
	case PEBS_1STL_CACHE_LOAD_MISS:

	    value[0] = (DS_BIT_0 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    break;

	case PEBS_2NDL_CACHE_LOAD_MISS:

	    value[0] = (DS_BIT_1 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    break;

	case PEBS_DTLB_LOAD_MISS:

	    value[0] = (DS_BIT_2 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    break;

	case PEBS_DTLB_STORE_MISS:

	    value[0] = (DS_BIT_2 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_1);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    break;

	case PEBS_DTLB_ALL_MISS:

	    value[0] = (DS_BIT_2 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0 | DS_BIT_1);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    break;

	case PEBS_MOB_LOAD_REPLAY:

	    value[0] = (DS_BIT_9 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    value[0] = ESCR_MOB_LOAD_REPLAY | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_MOB_ESCR0, (LL_INT *)&value);

	    break;

	case PEBS_SPLIT_LOAD:

	    value[0] = (DS_BIT_10 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_0);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    value[0] = ESCR_SPLIT_LOAD | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_SAAT_ESCR1, (LL_INT *)&value);

	    break;

	case PEBS_SPLIT_STORE:

	    value[0] = (DS_BIT_10 | DS_BIT_24 | DS_BIT_25);
    	    value[1] = 0;
    	    pentiumMsrSet (IA32_PEBS_ENABLE, (LL_INT *)&value);

	    value[0] = (DS_BIT_1);
    	    value[1] = 0;
    	    pentiumMsrSet (MSR_PEBS_MATRIX_VERT, (LL_INT *)&value);

	    value[0] = ESCR_SPLIT_STORE | (os ? ESCR_OS : ESCR_USR);
	    value[1] = 0;
	    pentiumMsrSet (MSR_SAAT_ESCR0, (LL_INT *)&value);

	    break;

	default:
	    return (ERROR);
	}

    value[0] = ESCR_REPLAY | (os ? ESCR_OS : ESCR_USR);
    value[1] = 0;
    pentiumMsrSet (MSR_CRU_ESCR2, (LL_INT *)&value);

    value[0] = CCCR_REPLAY;
    value[1] = 0;
    pentiumMsrSet (MSR_IQ_CCCR4, (LL_INT *)&value);

    return (OK);
    }