dbgstrlib.c

VxWorks BSP框架源代码包含头文件和驱动

/* dbgStrLib.c - Debug Store mechanism library */

/* Copyright 2001-2002 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01b,29oct02,hdn  allocated X86_EXT from stack instead.
01a,28jun01,hdn  written.
*/

/*
DESCRIPTION
This library provides Debug Store (DS) mechanism specific routines. 
The DS mechanism is introduced in the Pentium4 (P7) architecture.
The DS mechanism is used to collect two types of information that are 
branch records and precise event-based sampling records.  The availability 
of the DS mechanism in a processor is indicated with the DS feature flag 
(bit 21) returned by the CPUID instruction.

The DS save area is divided into three parts as follows: buffer
management area, branch trace store (BTS) buffer, and precise 
event-based sampling (PEBS) buffer.  The linear address of the 
first byte of the DS buffer management area is specified with the
IA32_DS_AREA MSR.  Here is the DS save area format:

      DS Buffer Management Area
      -----------------------
  0H  BTS buffer base          -> A
  4H  BTS index                -> B
  8H  BTS absolute maximum     -> C
  CH  BTS interrupt threshold
 10H  PEBS buffer base         -> X
 14H  PEBS index               -> Y
 18H  PEBS absolute maximum    -> Z
 1CH  PEBS interrupt threshold
 20H  PEBS counter reset (0-31)
 24H  PEBS counter reset (31-63)
 28H  reserved
      -----------------------

      BTS Buffer
      -----------------------
 A -> Branch Record 0
      Branch Record 1
      :
 B -> Branch Record current
      :
 C -> Branch Record n
      -----------------------

      PEBS Buffer
      -----------------------
 X -> PEBS Record 0
      PEBS Record 1
      :
 Y -> PEBS Record current
      :
 Z -> PEBS Record n
      -----------------------

The branch record is stored in the BTS buffer in the DS save area 
whenever a taken branch, interrupt, or exception is detected.
Here is the branch record format:
      0                    31
      -----------------------
  0H  Last Branch From EIP
  4H  Last Branch To EIP
  8H  Branch Predicted (bit 4)
      -----------------------

The PEBS record is stored in the PEBS buffer in the DS save area 
whenever a counter overflow occurs.  This record contains the 
architectural state of the processor (state of the 8 general purpose
registers, EIP register, and EFLAGS register) at the time of the event 
that caused the counter to overflow.  When the state information has 
been logged, the counter is automatically reset to a preselected value, 
and event counting begins again.  Here is the PEBS record format:
      0                    31
      -----------------------
  0H  EFLAGS
  4H  EIP (linear address)
  8H  EAX
  CH  EBX
 10H  ECX
 14H  EDX
 18H  ESI
 1CH  EDI
 20H  EBP
 24H  ESP
      -----------------------

When the DS mechanism is used, a 25 or 30 times slowdown can be expected
due to the effects of the trace store occurring on every taken branch.
The DS mechanism can be configured to either system mode or task mode.
In the system mode, only one DS save area is created and holds all the
BTS or PEBS records.  In the task mode, each task has its own dedicated
DS save area and holds the BTS or PEBS records while the task is executed.
The dedicated DS save area is created and deleted with the task.  And
switched as task switches.  This library provides following APIs:
.CS
  - to initialize this library.
    If the first or second parameter is zero, the default buffer size
    BTS_NBYTES_DEF or PEBS_NBYTES_DEF is used.  It is initialized to
    the system mode if the third parameter is TRUE.  Otherwise, task
    mode is used.
    STATUS dbgStrLibInit
    (
    UINT32 btsNbytes,	/@ BTS buffer size @/
    UINT32 pebsNbytes,	/@ PEBS buffer size @/
    BOOL   sysMode	/@ DS system mode @/
    )

  - to initialize the Debug Store (BTS + PEBS) buffer.
    The buffers are allocated if the pointers - that is 1st, 2nd and 5th
    params - are NULL.  
    DS_BUF_HEADER * dbgStrBufInit 
    (
    DS_BUF_HEADER * pH,		/@ Debug Store Buffer Header @/
    BTS_REC * btsBufAddr,	/@ BTS  buffer base @/
    UINT32 btsMaxOffset,	/@ BTS  absolute maximum @/
    UINT32 btsIntOffset,	/@ BTS  interrupt threshold @/
    PEBS_REC * pebsBufAddr,	/@ PEBS buffer base @/
    UINT32 pebsMaxOffset,	/@ PEBS absolute maximum @/
    UINT32 pebsIntOffset	/@ PEBS interrupt threshold @/
    )

  - to allocate the Debug Store buffers of the specified task.
    The first and second parameter of dbgStrLibInit() is used 
    for the BTS and PEBS buffer size respectively.  If the pTcb
    is NONE, the allocated buffer is set to the system DS config.
    STATUS dbgStrBufAlloc
    (
    WIND_TCB * pTcb	/@ pointer to the task's WIND_TCB @/
    )

  - to deallocate the Debug Store buffers of the specified task.
    If the pTcb is NONE, the allocated buffer for the system DS 
    config is deallocated.
    STATUS dbgStrBufFree
    (
    WIND_TCB * pTcb	/@ pointer to the task's WIND_TCB @/
    )

  - to configure the BTS/PEBS.
    This routine stores the configuration parameters in the DS_CONFIG
    structure.  If the first parameter is NONE, the system DS_CONFIG 
    structure is used.  If it is NULL, the current task's one is used.
    If the BTS interrupt mode is FALSE, the BTS buffer is used as a
    circular buffer.  This routine does not access any MSRs.
    STATUS dbgStrConfig 
    (
    WIND_TCB * pTcb,	/@ pointer to the task's WIND_TCB @/
    BOOL  btsEnable,	/@ BTS,  TRUE to enable BTS, FALSE to disable @/
    BOOL  pebsEnable,	/@ PEBS, TRUE to enable PEBS, FALSE to disable @/
    BOOL  btsIntMode,	/@ BTS,  TRUE to interrupt, FALSE to circular mode @/
    BOOL  btsBufMode,	/@ BTS,  TRUE to buffer, FALSE to send it on Bus @/
    INT32 pebsEvent,	/@ PEBS, event @/
    INT32 pebsMetric,	/@ PEBS, metric in the event @/
    BOOL  pebsOs,	/@ PEBS, TRUE if OS mode, otherwise USR mode @/
    LL_INT * pPebsValue	/@ PEBS, (reset) value in the counter @/
    )

  - to start/stop the BTS/PEBS with parameters set by dbgStrConfig().
    This routine calls dbgStrBtsModeSet(), dbgStrBtsEnable(),
    dbgStrPebsModeSet(), dbgStrPebsEnable().
    STATUS dbgStrStart 
    (
    WIND_TCB * pTcb,	/@ pointer to the task's WIND_TCB @/
    )

  - stop the Debug Store (BTS + PEBS) mechanism.
    This routine stops the BTS/PEBS mechanism if the specified task 
    is the current task.  Otherwise, it set the disable flag in the 
    DS configuration parameter of the task.
    This routine calls dbgStrBtsEnable() and dbgStrPebsEnable().
    STATUS dbgStrStop 
    (
    WIND_TCB * pTcb	/@ pointer to the task's WIND_TCB @/
    )

  - to setup the BTS mode.
    This routine set up the BTS MSRs with the specified mode.
    STATUS dbgStrBtsModeSet 
    (
    BOOL intMode,	/@ TRUE to generate int, FALSE to circular mode @/
    BOOL bufMode	/@ TRUE to store BTMs, FALSE to send BTMs on Bus @/
    )

  - to enable the BTS.
    This routine enables or disables the BTS.
    BOOL dbgStrBtsEnable 
    (
    BOOL enable		/@ TRUE to enable, FALSE to disable the BTS @/
    )

  - to setup the PEBS mode.
    This routine set up the PEBS MSRs with the specified mode.
    STATUS dbgStrPebsModeSet 
    (
    INT32 event,	/@ event @/
    INT32 metric,	/@ metric in the event @/
    BOOL os,		/@ TRUE if OS mode, otherwise USR mode @/
    LL_INT * pValue	/@ (reset) value in the counter @/
    )

  - to enable the PEBS.
    This routine enables or disables the PEBS.
    BOOL dbgStrPebsEnable
    (
    BOOL enable		/@ TRUE to enable, FALSE to disable the PEBS @/
    )
.CE

The show routine is provided and linked in if INCLUDE_SHOW_ROUTINES is
defined in the BSP.  The show routine dbgStrShow() has two parameters.
The first parameter is a pointer to the TCB.  If that is NONE, the system
BTS/PEBS information is shown.  If that is NULL, the current task's 
BTS/PEBS information is shown.  The second parameter specifies type of
interest.  It can be 0 for general information, 1 for BTS, 2 for PEBS.

In PEBS, the filtering events and cascading counters are not supported.
Also the logical processor specific PEBS in the Hyper Threading is not
supported.

INTERNAL
The BTS/PEBS interrupt hook routine is not used in this release.
A routine to transfer the BTS/PEBS records to the host tools maybe
connected, so that the BTS records would be shown in the source code
or the PEBS records can be displayed in GUI. 

SEE ALSO:
sysDbgStr.c and dbgStrShow.c
.I "Intel Architecture Software Developer's Manual"
*/

/* includes */

#include "vxWorks.h"
#include "taskLib.h"
#include "taskHookLib.h"
#include "regs.h"
#include "intLib.h"
#include "string.h"
#include "memPartLib.h"
#include "arch/i86/pentiumLib.h"
#include "arch/i86/perMonLib.h"
#include "arch/i86/dbgStrLib.h"
#include "drv/intrCtl/loApic.h"


/* defines */


/* externals */

IMPORT CPUID	sysCpuId;		/* CPUID structure */
IMPORT WIND_TCB * taskIdCurrent;	/* current taskId */


/* globals */

BOOL		dbgStrSysMode = FALSE;	/* TRUE for system mode */
DS_CONFIG	dbgStrCfg     = {0};	/* system DS config */
DS_CONFIG *	dbgStrCurrent = NULL;	/* current DS config */


/* locals */


/* prototypes */

LOCAL void   dbgStrCreateHook	(WIND_TCB * pNewTcb);
LOCAL void   dbgStrSwitchHook	(WIND_TCB * pOldTcb, WIND_TCB * pNewTcb);
LOCAL void   dbgStrDeleteHook	(WIND_TCB * pTcb);
LOCAL STATUS dbgStrPebsFrontEnd	(INT32 metric, BOOL os);
LOCAL STATUS dbgStrPebsExec	(INT32 metric, BOOL os);
LOCAL STATUS dbgStrPebsReplay	(INT32 metric, BOOL os);


/*******************************************************************************
*
* dbgStrLibInit - initialize the Debug Store library dbgStrLib
*
* This routine initializes the Debug Store library dbgStrLib.
* If the first or second parameter is zero, the default buffer size
* BTS_NBYTES_DEF or PEBS_NBYTES_DEF is used.  It is initialized to the 
* system mode if the third parameter is TRUE.  Otherwise, task mode is used.
*
* RETURNS: OK if Debug Store feature is supported, ERROR otherwise.
*/

STATUS dbgStrLibInit
    (
    UINT32 btsNbytes,	/* BTS buffer size */
    UINT32 pebsNbytes,	/* PEBS buffer size */
    BOOL   sysMode	/* DS system mode */
    )
    {
    INT32 value[2];		/* MSR 64 bits value */

    /* check if the Debug Store feature is supported */

    if ((sysCpuId.featuresEdx & CPUID_DTS) == 0)
        return (ERROR);

    /* check if the BTS and PEBS are available */

    pentiumMsrGet (IA32_MISC_ENABLE, (LL_INT *)&value);

    if ((value[0] & MSC_BTS_UNAVAILABLE) == 0)
        dbgStrCfg.btsAvailable = TRUE;

    if ((value[0] & MSC_PEBS_UNAVAILABLE) == 0)
        dbgStrCfg.pebsAvailable = TRUE;

    if (!dbgStrCfg.btsAvailable && !dbgStrCfg.pebsAvailable)
	return (ERROR);

    /* remember the BTS and PEBS buffer size, and the DS mode */

    dbgStrCfg.btsNbytes  = (btsNbytes == 0) ? BTS_NBYTES_DEF : btsNbytes;
    dbgStrCfg.pebsNbytes = (pebsNbytes == 0) ? PEBS_NBYTES_DEF : pebsNbytes;

    if ((dbgStrCfg.btsNbytes < BTS_NBYTES_MIN) || 
	(dbgStrCfg.pebsNbytes < PEBS_NBYTES_MIN))
	return (ERROR);

    dbgStrSysMode = sysMode;

    /* allocate and initialize the DS header, BTS/PEBS buffer */

    if (dbgStrBufAlloc ((WIND_TCB *)NONE) != OK)
	return (ERROR);

    /* set up the task create/switch/delete hook routines */

    if (!sysMode)
	{
        taskCreateHookAdd ((FUNCPTR)dbgStrCreateHook);
        taskSwitchHookAdd ((FUNCPTR)dbgStrSwitchHook);
        taskDeleteHookAdd ((FUNCPTR)dbgStrDeleteHook);
	}

    return (OK);
    }

/*******************************************************************************
*
* dbgStrBufInit - initialize the Debug Store (BTS + PEBS) buffer 
*
* This routine initializes the Debug Store (BTS + PEBS) buffer.  The buffers
* are allocated if the pointers - that is 1st, 2nd and 5th params - are NULL.
*
* RETURNS: address of Debug Store Buffer Header, or NULL if failed.
*/

DS_BUF_HEADER * dbgStrBufInit 
    (
    DS_BUF_HEADER * pH,		/* Debug Store Buffer Header */
    BTS_REC * btsBufAddr,	/* BTS  buffer base */
    UINT32 btsMaxOffset,	/* BTS  absolute maximum */
    UINT32 btsIntOffset,	/* BTS  interrupt threshold */
    PEBS_REC * pebsBufAddr,	/* PEBS buffer base */
    UINT32 pebsMaxOffset,	/* PEBS absolute maximum */
    UINT32 pebsIntOffset	/* PEBS interrupt threshold */
    )
    {
    UINT32 nRec;
    UINT32 nByte;

    /* allocate aligned Debug Store Buffer Header if pHeader is zero */

    if (pH == NULL)
	{
	pH = (DS_BUF_HEADER *)KMEM_ALIGNED_ALLOC (
	     		      sizeof (DS_BUF_HEADER), _CACHE_ALIGN_SIZE);
	if (pH == NULL)
	    return (NULL);
	}

    /* setup the Debug Store buffer management area for BTS */

    pH->btsBase      = btsBufAddr;
    pH->btsMax       = ((UINT32)btsBufAddr + btsMaxOffset) + 1;
    pH->btsThreshold = (UINT32)btsBufAddr + btsIntOffset;

    /* allocate aligned BTS buffer if btsBufAddr is zero */

    if ((dbgStrCfg.btsAvailable) && (btsBufAddr == NULL))
	{
	nRec = btsMaxOffset / sizeof (BTS_REC);
	nByte = nRec * sizeof (BTS_REC);
	
	/* override btsBase */

	pH->btsBase = (BTS_REC *)KMEM_ALIGNED_ALLOC (nByte, 
						     _CACHE_ALIGN_SIZE);
	if (pH->btsBase == NULL)
	    {
	    KMEM_FREE ((char *)pH);
	    return (NULL);
	    }

	/* override btsMax */

	pH->btsMax = ((UINT32)pH->btsBase + nByte) + 1;

	/* override btsThreshold */

	nRec = btsIntOffset / sizeof (BTS_REC);
	pH->btsThreshold = nRec * sizeof (BTS_REC) + (UINT32)pH->btsBase;
	}

    /* setup the Debug Store buffer management area for PEBS */

    pH->pebsBase      = pebsBufAddr;
    pH->pebsMax       = ((UINT32)pebsBufAddr + pebsMaxOffset) + 1;
    pH->pebsThreshold = (UINT32)pebsBufAddr + pebsIntOffset;

    /* allocate aligned PEBS buffer if pebsBufAddr is zero */

    if ((dbgStrCfg.pebsAvailable) && (pebsBufAddr == NULL))
	{
	nRec = pebsMaxOffset / sizeof (PEBS_REC);
	nByte = nRec * sizeof (PEBS_REC);
	
	/* override pebsBase */

	pH->pebsBase = (PEBS_REC *)KMEM_ALIGNED_ALLOC (nByte, 
						       _CACHE_ALIGN_SIZE);
	if (pH->pebsBase == NULL)
	    {
	    KMEM_FREE ((char *)pH->btsBase);
	    KMEM_FREE ((char *)pH);
	    return (NULL);
	    }

	/* override pebsMax */

	pH->pebsMax = ((UINT32)pH->pebsBase + nByte) + 1;

	/* override pebsThreshold */

	nRec = pebsIntOffset / sizeof (PEBS_REC);
	pH->pebsThreshold = nRec * sizeof (PEBS_REC) + (UINT32)pH->pebsBase;