cachecw400xlib.c

VxWorks BSP框架源代码包含头文件和驱动

/* cacheCW400xLib.c - LSI CW400x core cache management library */

/* Copyright 1996-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01i,17may02,pes  Before aborting cacheTextUpdate() on null pointer, check for
                 ENTIRE_CACHE.
01h,08may02,pes  Add protection against null pointers, zero counts, and
                 requests involving kseg1 in cacheXXXTextUpdate().
01g,16jul01,ros  add CofE comment
01f,28mar01,sru  remove CW400x-specific error codes
01e,10feb98,dra  changed Init, Enable & Disable to match CW4011
01d,10dec97,dra  added cache enable/disable funcs.
01c,17oct97,dra  made cache sizes, line masks depend on BSP.
01b,05may97,dra  fixed off by 1 error in end calc, fixed test for kseg1.
01a,09apr96,dra	 created
*/

/*
DESCRIPTION
This library contains architecture-specific cache library functions
for the LSI MIPS CW400x core architecture.  

ARCHITECTURE NOTES
General:
The CW400x cache is optional, as part of the BBCC building block for
the CW400x core.  The CC supports either direct-mapped or two-way set
associative I cache; D cache is always direct-mapped.  Icache can be
1k to 64kbytes (2 32kbyte sets); Dcache can be 1k to 32k.

The CW400x does allow locking of cache lines, by entering Software
Test Mode to set the lock bit. Cache lines can be written using loads
and stores in Software Test Mode.  Cache locking is not supported in
this library.

The cache always operates in write-through mode, so all clear
type operations map onto invalidate, and flush operations flush the
write buffer.

CW400x Specific:

For general information about caching, see the manual entry for cacheLib.

INCLUDE FILES: cacheLib.h

SEE ALSO: cacheCW400xALib, cacheLib
.I "LSI MiniRisc CW400x Microprocessor Core Technical Manual" */

#include "vxWorks.h"
#include "cacheLib.h"
#include "errnoLib.h"
#include "intLib.h"
#include "memLib.h"
#include "stdlib.h"
#include "errno.h"

/* CW400x specific defines */

/* Bits for BBCC config reg to enter Software Test Mode for cache mgmt */
#define	ICACHE_INV		(CFG_DCEN|CFG_ICEN|CFG_CMODE_ITEST)
#define IS1CACHE_INV		(CFG_DCEN|CFG_ICEN|CFG_CMODE_ITEST|CFG_IS1EN)
#define	DCACHE_INV		(CFG_DCEN|CFG_CMODE_DTEST)

/* Cache line size in bytes */
#define	CACHE_LINE_SIZE		(16)

/* externals */

IMPORT void    _cw4kCacheInvalidate(UINT configBits, UINT cacheLineMask, 
			       UINT startLine, UINT numLines);

IMPORT ULONG cacheCW400xicacheSet0Size;		/* BSP-specified */
IMPORT ULONG cacheCW400xicacheSet1;		/* BSP-specified */
IMPORT ULONG cacheCW400xdcacheSize;		/* BSP-specified */

/* forward declarations */

LOCAL STATUS	cacheCW400xEnable (CACHE_TYPE cache);
LOCAL STATUS	cacheCW400xDisable (CACHE_TYPE cache);
LOCAL void 	*cacheCW400xMalloc (size_t bytes);
LOCAL STATUS	cacheCW400xFree (void *pBuf);
LOCAL int	cacheCW400xWriteBufferFlush (void);
LOCAL STATUS	cacheCW400xInvalidate (CACHE_TYPE cache, void *pVirtAdrs, 
				       size_t bytes);
LOCAL void 	*cacheCW400xPhysToVirt (void *address);
LOCAL void 	*cacheCW400xVirtToPhys (void *address);
LOCAL STATUS	cacheCW400xTextUpdate (void *address, size_t bytes);
LOCAL ULONG	cacheLineMaskGet (ULONG cacheSize, ULONG cacheLineSize);
LOCAL void 	cacheAttributesGet (CACHE_TYPE cache, ULONG *pCacheSize,
				    ULONG *pCacheLineMask,
				    ULONG *pCacheEnableSetMask);

/* globals */

/* locals */

LOCAL ULONG icacheSize = 0;		/* computed during init */
LOCAL ULONG icacheLineMask = 0;		/* computed during init */
LOCAL ULONG icacheEnableSetMask = 0;	/* computed during init */
LOCAL ULONG dcacheSize = 0;		/* computed during init */
LOCAL ULONG dcacheLineMask = 0;		/* computed during init */
LOCAL ULONG dcacheEnableSetMask = 0;	/* computed during init */

/**************************************************************************
*
* cacheCW400xLibInit - initialize the LSI CW400x cache library
*
* This routine initializes the function pointers for the CW400x cache
* library.  The board support package can select this cache library 
* by calling this routine.
*
* RETURNS: OK.
*/

STATUS cacheCW400xLibInit
    (
    CACHE_MODE	instMode,	/* instruction cache mode */
    CACHE_MODE	dataMode	/* data cache mode */
    )
    {
    cacheLib.enableRtn = cacheCW400xEnable;		/* cacheEnable() */
    cacheLib.disableRtn = cacheCW400xDisable;		/* cacheDisable() */

    cacheLib.lockRtn = NULL;			/* cacheLock */
    cacheLib.unlockRtn = NULL;			/* cacheUnlock */

    cacheLib.flushRtn = cacheCW400xWriteBufferFlush;	/* cacheFlush() */
    cacheLib.pipeFlushRtn = cacheCW400xWriteBufferFlush;/* cachePipeFlush() */
    cacheLib.textUpdateRtn = cacheCW400xTextUpdate;/* cacheTextUpdate() */

    cacheLib.invalidateRtn = cacheCW400xInvalidate;/* cacheInvalidate() */
    cacheLib.clearRtn = cacheCW400xInvalidate;	/* cacheClear() */

    cacheLib.dmaMallocRtn = (FUNCPTR) cacheCW400xMalloc;/* cacheDmaMalloc() */
    cacheLib.dmaFreeRtn = cacheCW400xFree;		/* cacheDmaFree() */

    cacheLib.dmaVirtToPhysRtn = (FUNCPTR) cacheCW400xVirtToPhys;
    cacheLib.dmaPhysToVirtRtn = (FUNCPTR) cacheCW400xPhysToVirt;

    /* Setup cacheFuncs variables */
    cacheDataMode	= dataMode;		/* save dataMode for enable */
    cacheMmuAvailable	= TRUE;			/* mmu support is provided */
    cacheDataEnabled = TRUE;			/* d-cache is currently on */
    cacheFuncsSet ();				/* update cache func ptrs */

    /* Disable the caches - do this first. */
    cacheCW400xDisable(DATA_CACHE);
    cacheCW400xDisable(INSTRUCTION_CACHE);

    /* validate provided icache sizes, and compute useful constants */
    icacheSize = cacheCW400xicacheSet0Size;

    /* not valid to have set1 present if set0 size is 0 */
    if ((icacheSize == 0) && cacheCW400xicacheSet1) 
	{
	return (ERROR);
	}

    icacheLineMask = cacheLineMaskGet (icacheSize, CACHE_LINE_SIZE);
    if (icacheSize != 0 && icacheLineMask == 0)
        {
	return (ERROR);
	}
    icacheEnableSetMask = (cacheCW400xicacheSet0Size ? CFG_ICEN : 0) |
                          (cacheCW400xicacheSet1 ? CFG_IS1EN : 0);

    /* validate provided dcache sizes, and compute useful constants */
    dcacheSize = cacheCW400xdcacheSize;
    dcacheLineMask = cacheLineMaskGet (dcacheSize, CACHE_LINE_SIZE);
    if (dcacheSize != 0 && dcacheLineMask == 0)
        {
	return (ERROR);
	}
    dcacheEnableSetMask = (cacheCW400xdcacheSize ? CFG_DCEN : 0);

    /* Invalidate the caches */
    cacheCW400xInvalidate(DATA_CACHE, 0, ENTIRE_CACHE);
    cacheCW400xInvalidate(INSTRUCTION_CACHE, 0, ENTIRE_CACHE);

    return (OK);
    }

/**************************************************************************
*
* cacheCW400xEnable - enable the specificed cache.
*
* RETURNS: OK, or ERROR if the cache type is invalid.
*/

LOCAL STATUS	cacheCW400xEnable
    (
    CACHE_TYPE	cache			/* Cache to enable */
    )
    {
    int oldLevel;
    volatile ULONG *config = CFG4000_REG;

    switch (cache)
	{
	case DATA_CACHE:
	    oldLevel = intLock ();
	    cacheCW400xInvalidate(DATA_CACHE, 0, ENTIRE_CACHE);
	    *config |= dcacheEnableSetMask;
	    intUnlock (oldLevel);
	    break;

	case INSTRUCTION_CACHE:
	    oldLevel = intLock ();
	    cacheCW400xInvalidate(INSTRUCTION_CACHE, 0, ENTIRE_CACHE);
	    *config |= icacheEnableSetMask;
	    intUnlock (oldLevel);
	    break;

	default:
	    errno = S_cacheLib_INVALID_CACHE;
	    return (ERROR);
	}
    return (OK);
    }

/**************************************************************************
*
* cacheCW400xDisable - enable the specificed cache.
*
* RETURNS: OK, or ERROR if the cache type is invalid.
*/

LOCAL STATUS	cacheCW400xDisable
    (
    CACHE_TYPE	cache			/* Cache to disable */
    )
    {
    int oldLevel;
    volatile ULONG *config = CFG4000_REG;

    /*
     * Note that the xcacheEnableSetMask variables are not used for
     * disabling the caches.  This is because while the caches may not
     * be enabled in the BSP, the still need to be disabled here.
     */
    switch (cache)
	{
	case DATA_CACHE:
	    oldLevel = intLock ();
	    *config &= ~CFG_DCEN;
	    /*
	     * At this point we would normally set cacheDataEnabled false,
	     * and then call cacheFuncsSet() to update the cache pointers,
	     * but problems have been observed with some ethernet drivers
	     * if the cache "DMA malloc" routines are not used to allocate
	     * buffers for MIPS.
	     */
	    intUnlock (oldLevel);
	    break;

	case INSTRUCTION_CACHE:
	    oldLevel = intLock ();
	    *config &= ~(CFG_ICEN | CFG_IS1EN);
	    intUnlock (oldLevel);
	    break;

	default:
	    errno = S_cacheLib_INVALID_CACHE;
	    return (ERROR);
	}
    return (OK);
    }

/**************************************************************************