excalib.s

VxWorks BSP框架源代码包含头文件和驱动

* This routine is not callable!!  This routine does not include save and
* restore of floating point state.
*

* NOMANUAL

* void excCache()

*/
#define STKSIZE	256
	.comm cache_xcp, ESTKSIZE+STKSIZE

	.ent	excCache
excCache:
	/*
	 * Low-level handler only saved $at and $k0, give ourselves
	 * more legroom.
	 */
	la	k0,cache_xcp+STKSIZE
	or	k0,K1BASE
	SW	sp,E_STK_SP(k0)
	move	sp,k0
	SW	v0,E_STK_V0(sp)
	SW	a0,E_STK_A0(sp)
	SW	a1,E_STK_A1(sp)
	SW	a2,E_STK_A2(sp)
	mfc0	v0,C0_CACHEERR
	mfc0	a2,C0_TAGLO		# save taglo
	HAZARD_CP_READ
	and	a0,v0,CACHEERR_BUS	# sysAD bus error?
	bnez	a0,mem_err

	and	a0,v0,CACHEERR_LEVEL	# secondary cache error?
	bnez	a0,scache_err

pcache_err:
	/* error is in one or both primary caches */
	/* generate cache address to use for cacheops */
	and	a0,v0,CACHEERR_SIDX_MASK & ((1<<CACHEERR_PIDX_SHIFT)-1)
	and	a1,v0,CACHEERR_PIDX_MASK
	sll	a1,CACHEERR_PIDX_SHIFT
	or	a0,a1			# $a0 = primary cache index
	addu	a0,K0BASE

	/* determine which cache */
	and	a1,v0,CACHEERR_TYPE
	bnez	a1,pdcache

picache:
	/* zap primary instruction cache line */
	mtc0	zero,C0_TAGLO
	HAZARD_CACHE_TAG
        cache   Index_Store_Tag_I,0(a0)
	b	fixed

pdcache:
	/* give up on a Dirty Exclusive line */
        cache   Index_Load_Tag_D,0(a0)
	HAZARD_CACHE_TAG
	mfc0	a1,C0_TAGLO
	HAZARD_CP_READ
	and	a1,1<<TAG_PSTATE_SHIFT
	bnez	a1,giveup

	/* we can now zap the line */
	mtc0	zero,C0_TAGLO
	HAZARD_CACHE_TAG	
        cache   Index_Store_Tag_D,0(a0)

	/*
	 * cache error appears to be fixed
	 */
fixed:	
	HAZARD_CACHE_TAG
	mtc0	a2,C0_TAGLO	 	# restore taglo
	LW	v0,E_STK_V0(k0)	
	LW	a0,E_STK_A0(k0)	
	LW	a1,E_STK_A1(k0)	
	LW	a2,E_STK_A2(k0)	
	j	ra

mem_err:
	/* not yet implemented */

scache_err:
	/* not yet implemented */

giveup:	
	/* protect ourselves from any more cache errors */
	mfc0	v0,C0_SR
	HAZARD_CP_READ
	or	v0,SR_DE
	mtc0	v0,C0_SR
	HAZARD_CP_WRITE
	
	/* stuff a message in the catastrophic message area */

	lw	a1,sysExcMsg
	beqz	a1,1f
	la	a0,cacheMsg
	jal	strcpy
1:	li	a0,BOOT_NO_AUTOBOOT
	jal	reboot
	b	1b
	j	ra
	.end	excCache

	.rdata
cacheMsg:
	.ascii	"Fatal cache error"
	.byte	0
	.text
#endif

#ifdef _WRS_R3K_EXC_SUPPORT
/*********************************************************************
*
* excNormVec - Instructions to load at the r3000 normal exception vector
*
* These instructions are copied to 0x80000080, the normal exception vector
* by the startup routine excVecInit.  We must use the assembler pseudo op .noat 
* so the la instruction will not use the at register and mess with process 
* state.  The .set noreorder takes instruction reorder control away from the
* assembler, and puts it in our hands.  We are using load address and jump to
* register so that we may run vxWorks out of prom (see j, and jal instruction
* definitions).
*
* NOMANUAL

* void excNormVec()
*/

	.ent	excNormVec
	.set	noreorder
	.set	noat
excNormVec:
	mfc0	k0, C0_CAUSE		/* grab cause register	*/
	HAZARD_CP_READ
	lw	k1, areWeNested		/* grab value in delay slot*/
	andi	k0, CAUSE_EXCMASK	/* look at exception bits */
	bne	k0, zero, 1f		/* zero == interrupt	  */
	nop
	la	k0, excIntStub
	j	k0			/* jump to interrupt handler */
	nop
1:	la	k0, excStub
	j	k0			/* jump to exception handler */
	nop
excNormVecEnd:
	.set	at
	.set	reorder
	.end	excNormVec

	.data
	.align	4
excNormVecSize:
	.word	excNormVecEnd-excNormVec
	.text

#endif

/*********************************************************************
*
* excTlbVec - Instructions to load at the r4000 tlb exception vector
*
* These instructions are copied to 0x80000000, the Tlb exception vector
* by the startup routine excVecInit.  We must use the assembler pseudo op
* .noat so the la instruction will not use the at register and mess with
* process state.  The .set noreorder takes instruction reorder control away
* from the assembler, and puts it in our hands.
*
* To handle tlb exceptions that are funneled to this vector
* we do not have to save state fully.  Since vxworks does not
* use the tlb, we leave it as a common handler, saving full state
* for panics.  If we did use the tlb, this should have its own 
* special vector.  We are using load address and jump to register 
* so that we may run vxWorks out of prom (see j, and jal instruction
* definitions).
*
* NOMANUAL

* void excTlbVec()
*/

	.ent	excTlbVec
	.set	noreorder
	.set	noat
excTlbVec:
	la	k0, excStub
	j	k0				/* jump to exception handler */
	nop
excTlbVecEnd:
	.set	at
	.set	reorder
	.end	excTlbVec

	.data
	.align	4
excTlbVecSize:
	.word	excTlbVecEnd-excTlbVec
	.text

#ifndef _WRS_R3K_EXC_SUPPORT
/*********************************************************************
*
* excXtlbVec - Instructions to load at the r4000 Xtlb exception vector
*
* These instructions are copied to 0x80000080, the Xtlb exception vector
* by the startup routine excVecInit.  We must use the assembler pseudo op
* .noat so the la instruction will not use the at register and mess with
* process state.  The .set noreorder takes instruction reorder control away
* from the assembler, and puts it in our hands.
*
* To handle tlb exceptions that are funneled to this vector
* we do not have to save state fully.  Since vxworks does not
* use the tlb, we leave it as a common handler, saving full state
* for panics.  If we did use the tlb, this should have its own 
* special vector.  We are using load address and jump to register 
* so that we may run vxWorks out of prom (see j, and jal instruction
* definitions).
*
* NOMANUAL

* void excXtlbVec()
*/

	.ent	excXtlbVec
	.set	noreorder
	.set	noat
excXtlbVec:
	la	k0, excStub
	j	k0				/* jump to exception handler */
	nop
excXtlbVecEnd:
	.set	at
	.set	reorder
	.end	excXtlbVec

	.data
	.align	4
excXtlbVecSize:
	.word	excXtlbVecEnd-excXtlbVec
	.text
#endif /* _WRS_R3K_EXC_SUPPORT */

#ifndef _WRS_R3K_EXC_SUPPORT
/*********************************************************************
*
* excCacheVec - Instructions to load at the r4000 cache exception vector
*
* These instructions are copied to 0xa0000100, the cache exception vector
* by the startup routine excVecInit.  We must use the assembler pseudo op
* .noat so the la instruction will not use the at register and mess with
* process state.  The .set noreorder takes instruction reorder control away
* from the assembler, and puts it in our hands.
* When a cache excption takes place, KUSEG is replaced by an unmapped
* uncached area that can be accessed using 0 based addressing.  We 
* save some registers in fixed locations and then attempt to fix the cache
* error.
*
* NOMANUAL

* void excCacheVec()
*/

/* save just below general exception handler */
#define AT_SAVE	+(0x180-8)
#define K0_SAVE	+(0x180-16)
#define RA_SAVE	+(0x180-24)

	.ent	excCacheVec
	.set	noreorder
	.set	noat
excCacheVec:
	SW	AT,AT_SAVE(zero)
	SW	k0,K0_SAVE(zero)
	SW	ra,RA_SAVE(zero)
	.set	at
	la	k0,excCache
	or	k0,K1BASE		# must stay uncached
	jal	k0
	nop
	.set	noat
	LW	AT,AT_SAVE(zero)
	LW	k0,K0_SAVE(zero)
	LW	ra,RA_SAVE(zero)
	eret
	nop
excCacheVecEnd:
	.set	at
	.set	reorder
	.end	excCacheVec

	.data
	.align	4
excCacheVecSize:
	.word	excCacheVecEnd-excCacheVec
	.text

/*********************************************************************
*
* excNormVec - Instructions to load at the r4000 normal exception vector
*
* These instructions are copied to 0x80000180, the normal exception vector
* by the startup routine excVecInit.  We must use the assembler pseudo op .noat 
* so the la instruction will not use the at register and mess with process 
* state.  The .set noreorder takes instruction reorder control away from the
* assembler, and puts it in our hands.  We are using load address and jump to
* register so that we may run vxWorks out of prom (see j, and jal instruction
* definitions).
*
* NOMANUAL

* void excNormVec()
*/

	.ent	excNormVec
	.set	noat
excNormVec:
	mfc0	k0, C0_CAUSE		/* grab cause register	*/
	HAZARD_CP_READ
	lw	k1, areWeNested		/* grab value in delay slot*/
	andi	k0, CAUSE_EXCMASK		/* look at exception bits */
	bne	k0, zero, 1f		/* zero == interrupt	  */
	la	k0, excIntStub
	j	k0			/* jump to interrupt handler */
1:	la	k0, excStub
	j	k0			/* jump to exception handler */
excNormVecEnd:
	.set	at
	.end	excNormVec

	.data
	.align	4
excNormVecSize:
	.word	excNormVecEnd-excNormVec
	.text

#endif /* !_WRS_R3K_EXC_SUPPORT */