excalib.s

VxWorks BSP框架源代码包含头文件和驱动

/* excALib.s - assembly language exception handling stubs */

/* Copyright 1984-2001 Wind River Systems, Inc. */
	.data
	.globl	copyright_wind_river

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
04k,19jun02,pes  SPR 78857: Prevent interrupt race when clearing EXL bit.
04j,18jan02,agf  add explicit align directive to data section(s)
04i,30nov01,pes  Fix SPR 26903: k0 may be overwritten during interrupt service
                 in restoreVolatile
04h,16jul01,ros  add CofE comment
04g,09jul01,agf  fix logic for spurious extended interrupt
04f,07jun01,agf  Add RM7000 extended interrupt support to WindView
                 instrumentation
04f,12jun01,mem  Fix SR handling in return from exception case.
04e,16feb01,tlc  Perform HAZARD review.
04d,15feb01,pes  Complete change indicated in 04c.
04c,15feb01,pes  Avoid reserved instruction exception in restoreVolatile
                 caused by ctc0 instruction in branch delay slot after
                 checking for extended interrupts.
04b,14feb01,zmm  Change .sdata to .data.
04a,13feb01,pes  Add support for RM7000 extended interrupts.
03z,19dec00,pes  Adapt to MIPS32/MIPS64 CPU architectures
03y,19jun00,dra  work around 5432 branch bug
03x,19jan99,dra  added CW4000, CW4011, VR4100, VR5000 and VR5400 support.
03w,30apr99,nps  remove inclusion of evtBufferLib.h
03v,12aug98,kkk  fixed bug in saving FPCSR in excStub. (SPR# 20669)
03u,16apr98,pr   added WindView 20 support.
03t,04apr97,kkk	 fixed excStub to not use k0 and k1 outside of 
		 non-interruptible sections (SPR# 8317)
03s,07mar97,tam  fixed problem when testing SR[CU1] bit (spr #8147)
03r,16dec96,kkk  took out duplicate code.
03q,12dec96,tam  added code to excStub to save FPCSR register (spr #7631).
03p,14oct96,kkk  added R4650 support.
03p,30jul96,kkk  in restoreVolatile, make sure all ints are masked out before
		 reenabling interrupts. (SPR# 4574)
03o,22jul96,pr   added instrumentation
		 moved state save to beginning of excIntStub
03n,08dec94,caf  moved check for spurious interrupt.
03m,12oct94,caf  added support for user prioritized interrupts
		 in excIntStub() (SPR #3714).
03l,19oct93,cd   added R4000 support.
03k,29sep93,caf  undid fix for SPR #2362 due to nested interrupt problem.
03j,07jul93,yao  fixed to read cause register only once (SPR #2362).
                 changed copyright notice.
03i,01oct92,ajm  merge missed changes for spurious interupts, 
		  general cleanup and doc
03h,05jun92,ajm  5.0.5 merge, notice mod history changes
03g,26may92,rrr  the tree shuffle
03f,05nov91,ajm  now use areWeNested to check for interrupt nesting, this
		  allows intCnt to be used for watchDogs.
03e,04oct91,rrr  passed through the ansification filter
                  -changed VOID to void
                  -changed ASMLANGUAGE to _ASMLANGUAGE
                  -changed copyright notice
03d,16jul91,ajm  changed excNormVec to fill more pipeline slots by loading
		  intCnt which was previously done in excIntStub.
03c,08jul91,ajm  changed how excStub reenables interrupts for consistency
		  and debugger.
03b,28may91,ajm  minor changes due to order change in REG_SET
03a,28feb91,ajm  created 5.0 version from 4.02 source
02p,13dec90,ajm  added deterministic hash search to find out which interrupt
		  is bugging us.  This blows away the software prioritization
		  of interrupts in the Prio table (see intR3kLib).  Presently
		  this is ifdefd' with DETERMINISTIC in both this module, and
		  intR3kLib.c so we can go back if we chose.
02o,19nov90,ajm  interleaved instructions to eliminate nop dead cycles
02n,01oct90,ajm  fixed interrupt nesting problem by using SR mask instead
		  of cause mask in excIntStub (PA resolution)
02m,19sep90,ajm  added excIntToExc routine to change thread of floating
		  point interrupts
02l,24aug90,ajm  placed nop before reenabling interrupts with k1 in excStub.
02k,09aug90,ajm  changed j in excUtlbVec, and excGenVec to la and jr
		  so that we can use ram exception vectors while running
		  out of prom.
02j,30jul90,ajm  placed the AT register in the frame of the gp regs 
		  for exceptions so that taskRegsSet and Get make mods
		  correctly in debug.  Thus it is duplicated across
		  the frame.
02i,18jun90,ajm  changed all references to k0 to be in non-interruptible
		  sections.  This is because intExit needs two registers
		  to return with (k0,k1).  Use of k0 in a preempible section
		  would cause havoc.
02h,07jun90,ajm  moved status register manipulation with rfe to soley this
		  module.  This eliminates the need for the previous change.
02g,06jun90,ajm  changed status register manipulation in intExcStub to always
		  enable interrupts by oring SR_IEC in the lsb.  This is done
		  because we no longer use rfe in windLoadContext.
02f,06jun90,ajm  corrected sp save (+ to -) for nested interrupts and exceptions
02e,03jun90,ajm  added restore from exceptions for breakpoints
02d,23may90,ajm  separated excCmnStub into excIntStub and excStub since
		  interrupts and exceptions use different stacks.  Also
		  needed to change excUtlbVec, and excNormVec to make
		  changes work.
02c,08may90,ajm  added stack space for jalr in excCmnStub for up to 4 
		  passed parameters (see esfR3k.h)
02b,01may90,ajm  got rid of gp references, really don't need them if
		  everything is one image
02a,09apr90,ajm  ported to mips r3000
01i,17jan89,jcf  fixed bug in excIntStub; intExit no longer takes d0 on stack.
01i,13feb88,dnw  added .data before .asciz above, for Intermetrics assembler.
01h,01nov87,jcf	 added code in excStub to retry an instruction
01g,24mar87,dnw  added .globl for excExcHandle.
		 documentation.
01f,26feb87,rdc  modifications for VRTX 3.2.
01e,21dec86,dnw  changed to not get include files from default directories.
01d,31oct86,dnw  Eliminated magic f/b numeric labels which mitToMot can't
		   handle.
		 Changed "moveml" instructions to use Motorola style register
		   lists, which are now handled by "aspp".
		 Changed "mov[bwl]" to "move[bwl]" for compatiblity w/Sun as.
01c,26jul86,dnw  changed 68000 version to use BSR table w/ single handler rtn.
01b,03jul86,dnw  documentation.
01a,03apr86,dnw  extracted from dbgALib.s
*/

/*
DESCRIPTION
This module contains the assembly language exception handling stub excStub, 
along with the interrupt handling stub excIntStub.
They are connected directly to the MIPS exception vectors by software.
They simply set up an appropriate environment and then call the appropriate
routine in excLib.

There are no user-callable routines in this module.
*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "private/eventP.h"
#include "asm.h"
#include "esf.h"
#include "sysLib.h"

#define C0_1_IC	$20			/* Interrupt control (CP0 set 1) */

#define IC_IMASKSHIFT         8         /* offset of ICR intrpt enables  */
#define IC_IMASK              0xff00    /* mask   of ICR intrpt enables  */
#define CAUSE_EXTMASKSHIFT    8         /* offset to align extended pending  */
                                        /*   bits with standard pending bits */

	/* internal */

	.globl	excBsrTbl	/* int/exception handler table	*/
	.globl	excStub		/* exception dispatch stub	*/
	.globl	excIntStub	/* interrupt dispatch stub	*/
	.globl	excNormVec	/* Normal exc/int vector	*/
	.globl	excNormVecSize	/* Normal exc/int vector size */
	.globl	excTlbVec	/* Tlb exception vector */
	.globl	excTlbVecSize	/* Tlb exception vector size */
#ifndef _WRS_R3K_EXC_SUPPORT
	.globl	excXtlbVec	/* Xtlb exception vector */
	.globl	excXtlbVecSize	/* Xtlb exception vector size */
	.globl	excCacheVec	/* Cache exception vector */
	.globl	excCacheVecSize	/* Cache exception vector size */
#endif

	/* external */

	.extern	sysHashOrder		/* address of hash table */
	.extern	intCnt			/* interrupt depth	*/
	.extern	areWeNested		/* Boolean for int nesting */
	.extern	vxIntStackBase		/* interrupt stack base */
	.extern	errno			/* unix like errno */

#ifdef WV_INSTRUMENTATION
	.extern	_func_evtLogT0			/* _func_evtLogT0 func ptr */
	.extern	_func_trgCheck			/* _func_trgCheck func ptr */
	.extern	evtAction    			
	.extern	wvEvtClass		
	.extern	trgEvtClass			
#endif /* WV_INSTRUMENTATION */

	.text
	.set	reorder

/******************************************************************************
*
* mipsIntHookSet - set the MIPS interrupt enter/exit hooks
*
*
*
* NOTE
*
* INTERNAL
*

* void mipsIntHookSet(FUNCPTR enterHook, void exitHook)

*/
	.data
	.align	4
	.globl _func_mipsIntHookEnter
_func_mipsIntHookEnter:
	.word	0
	.globl _func_mipsIntHookExit
_func_mipsIntHookExit:
	.word	0
	.text

	.globl	mipsIntHookSet
	.ent	mipsIntHookSet
mipsIntHookSet:
	sw	a0, _func_mipsIntHookEnter
	sw	a1, _func_mipsIntHookExit
	j	ra
	.end	mipsIntHookSet

/******************************************************************************
*
* mipsExtndIntEnable/mipsExtndIntDisable - enable/disable
*  RM7000 extended interrupt support.
*
*
*
* NOTE
*
* INTERNAL
*
* void mipsExtndIntEnable(void)
* void mipsExtndIntDisable(void)
*
*/
	.data
	.align	4
intStubSelect:	
	.word	0
	
	.text

	.globl	mipsExtndIntEnable
	.ent	mipsExtndIntEnable
mipsExtndIntEnable:	
	li	t0,1
	sw	t0, intStubSelect
	j	ra
	.end	mipsExtndIntEnable
	
	.globl	mipsExtndIntDisable
	.ent	mipsExtndIntDisable
mipsExtndIntDisable:	
	li	t0,0
	sw	t0, intStubSelect
	j	ra
	.end	mipsExtndIntDisable

/*******************************************************************************
*
* excStub - catch and dispatch exceptions
*
* This is the exception handler that is pointed to by the exception
* vector at address 0x80000080, the general exception vector.  
* In this routine we take care of fully saving state, and jumping to the 
* appropriate routines.  On exit from handling we also return 
* here to restore state properly.
*

* NOTE
* For now the utlb vector points here also.
*
* This routine is not callable!!  This routine does not include save and
* restore of floating point state.
*
* INTERNAL
* The goal here is to turn interrupts back on a quickly as possible.
* Some guidelines we have followed are that k0 and k1 can ONLY be used in 
* non-interruptible sections.  Also, before we turn interrupts back on we 
* must save as a minimum the state of the processor that changed upon 
* interrupt generation (volatile registers).  Volatile registers include
* the EPC, CAUSE, STATUS, and BADVA.  Also saved before interrupts are
* enabled, are the sp, and at regs.  These registers are not volatile, but
* used in reading and saving volatile registers.  All registers are saved 
* for proper state display.
*
* NOMANUAL

* void excStub()

*/

	.globl	excStub
	.ent	excStub
excStub:
	.set	noat
	/* we are operating on the task stack at this point */
	SW	sp, E_STK_SP-ESTKSIZE(sp) /* save sp in new intstk frame */
	subu	sp, ESTKSIZE		/* make new exc stk frame	*/
	SW	AT,E_STK_AT(sp)		/* save asmbler resvd reg	*/
	SW	v0,E_STK_V0(sp)		/* save func return 0, used
					   to hold masked cause		*/
	.set	at
	HAZARD_VR5400
	mfc0	k1, C0_BADVADDR		/* read bad VA reg	*/
	mfc0	k0, C0_EPC		/* read exception pc	*/
	HAZARD_CP_READ
	sw	k1, E_STK_BADVADDR(sp)	/* save bad VA on stack	*/
	sw	k0, E_STK_EPC(sp)	/* save EPC on stack	*/
	mfc0	v0, C0_CAUSE		/* read cause register	*/
	mfc0	k1, C0_SR		/* read status register	*/
	HAZARD_CP_READ
	sw	v0, E_STK_CAUSE(sp)	/* save cause on stack	*/
	andi	v0, CAUSE_EXCMASK	/* mask to get the exception cause
					   v0 preserved till jal */
	sw	k1, E_STK_SR(sp)	/* save status on stack	*/

#ifndef SOFT_FLOAT
        /* Now save the FP status register if coprocessor 1 is enabled.
         * We need to do this before enabling exceptions, otherwise,
         * another fpp exception could come in and trash the current
         * state.
         */

        and     k0, k1, SR_CU1          /* coprocessor 1 enabled? */
        beq     k0, zero, excNoFpu
        cfc1    k0, C1_SR               /* read FPCSR register */
	HAZARD_CP_READ
        sw      k0, E_STK_FPCSR(sp)     /* save FPCSR on stack */
        and     k0, k0, ~FP_EXC_MASK    /* clear FPCSR bits    */
        ctc1    k0, C1_SR
	HAZARD_CP_WRITE
#endif	/* !SOFT_FLOAT */

excNoFpu:
#ifdef _WRS_R3K_EXC_SUPPORT
	and	k0, k1, ~SR_KUMSK	/* k0 gets hi order 26 bits */
	and	k1, SR_KUMSK		/* k1 get low order 6 bits */
	srl	k1, 2			/* previous interrupt state */
	or	k1, k0			/* put them together */
#endif
	HAZARD_VR5400
#ifndef _WRS_R3K_EXC_SUPPORT
	mtc0	k1, C0_SR		/* SPR 78857: ensure ints masked */