cachetx49alib.s

VxWorks BSP框架源代码包含头文件和驱动

*

* void cacheTx49RomTextUpdate (void)

*/
	.ent	cacheTx49RomTextUpdate
FUNC_LABEL(cacheTx49RomTextUpdate)
	SETFRAME(cacheTx49RomTextUpdate, 0)
	subu	sp, FRAMESZ(cacheTx49RomTextUpdate)
	SW	ra, FRAMERA(cacheTx49RomTextUpdate)(sp)	/* save return address */
	sw	a0, cacheTx49ICacheSize
	sw	a1, cacheTx49ICacheLineSize
	sw	a2, cacheTx49DCacheSize
	sw	a3, cacheTx49DCacheLineSize
	jal	cacheTx49PTextUpdateAll
	LW	ra, FRAMERA(cacheTx49RomTextUpdate)(sp)	/* restore return address */
	addu	sp, FRAMESZ(cacheTx49RomTextUpdate)
	j	ra
	.end	cacheTx49RomTextUpdate
	
/******************************************************************************
*
* cacheTx49PTextUpdate - text update for entire cache.
*
* RETURNS: N/A
*

* void cacheTx49PTextUpdate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx49PTextUpdate
FUNC_LABEL(cacheTx49PTextUpdate)

	/* run from kseg1 */

	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	

	/* Save parameters */

	move	t0,a0           # virtual address
	move	t1,a1		# number of bytes to invalidate

	/* Check for primary data cache */

	lw	a2,cacheTx49DCacheSize
	blez	a2,99f

	/* Flush-invalidate primary data cache */

	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
99:

	/* replace parameters */

	move	a0,t0		# virtual address
	move	a1,t1		# number of bytes to invalidate
	
	/* Check for primary instruction cache */

	lw	a2,cacheTx49ICacheSize
	blez	a2,99f
	
	/* Invalidate primary instruction cache */

	lw	a3,cacheTx49ICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
99:
	j	ra
	.end	cacheTx49PTextUpdate


/*******************************************************************************
*
* cacheTx49DCFlushInvalidateAll - flush and invalidate entire Tx49 data cache
*
* RETURNS: N/A
*

* void cacheTx49DCFlushInvalidateAll (void)

*/
	.ent	cacheTx49DCFlushInvalidateAll
FUNC_LABEL(cacheTx49DCFlushInvalidateAll)
	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	li	a0,K0BASE
	srl	a2,2		# 4 ways are process for each address
	move	a1,a2
	icacheop_all_ways(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx49DCFlushInvalidateAll

/*******************************************************************************
*
* cacheTx49DCFlushInvalidate - flush and invalidate Tx49 data cache locations
*
* RETURNS: N/A
*

* void cacheTx49DCFlushInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx49DCFlushInvalidate
FUNC_LABEL(cacheTx49DCFlushInvalidate)
	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
99:	j	ra
	.end	cacheTx49DCFlushInvalidate


/*******************************************************************************
*
* cacheTx49DCInvalidateAll - invalidate entire Tx49 data cache.
*
* For the _tx49xx family, this function does a flush invalidate due to the
* lack of an Indexed Invalidate operation in the CACHE instruction
*
* RETURNS: N/A
*

* void cacheTx49DCInvalidateAll (void)

*/
	.ent	cacheTx49DCInvalidateAll
FUNC_LABEL(cacheTx49DCInvalidateAll)
1:	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	li	a0,K0BASE
	srl	a2,2		# 4 ways are process for each address
	move	a1,a2
	icacheop_all_ways(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx49DCInvalidateAll

/*******************************************************************************
*
* cacheTx49DCInvalidate - invalidate Tx49 data cache locations
*
* RETURNS: N/A
*

* void cacheTx49DCInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx49DCInvalidate
FUNC_LABEL(cacheTx49DCInvalidate)
1:	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
99:	j	ra
	.end	cacheTx49DCInvalidate

/*******************************************************************************
*
* cacheTx49DCFlushAll - flushes entire Tx49 data cache.
*
* For the _tx49xx family, this function does a flush invalidate due to the
* lack of an Indexed Flush operation in the CACHE instruction
*
* RETURNS: N/A
*

* void cacheTx49DCFlushAll (void)

*/
	.ent	cacheTx49DCFlushAll
FUNC_LABEL(cacheTx49DCFlushAll)
1:	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	li	a0,K0BASE
	srl	a2,2		# 4 ways are process for each address
	move	a1,a2
	icacheop_all_ways(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx49DCFlushAll

/*******************************************************************************
*
* cacheTx49DCFlush - flush Tx49 data cache locations
*
* RETURNS: N/A
*

* void cacheTx49DCFlush
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx49DCFlush
FUNC_LABEL(cacheTx49DCFlush)
1:	lw	a2,cacheTx49DCacheSize
	blez	a2, 99f
	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_D)
99:	j	ra
	.end	cacheTx49DCFlush

/*******************************************************************************
*
* cacheTx49ICInvalidateAll - invalidate entire Tx49 instruction cache
*
* RETURNS: N/A
*

* void cacheTx49ICInvalidateAll (void)

*/
	.ent	cacheTx49ICInvalidateAll
FUNC_LABEL(cacheTx49ICInvalidateAll)
	lw	a2,cacheTx49ICacheSize
	blez	a2,99f
	lw	a3,cacheTx49ICacheLineSize
	li	a0,K0BASE
	srl	a2,2		# 4 ways are process for each address
	move	a1,a2
	icacheop_all_ways(a0,a1,a2,a3,Index_Invalidate_I)

99:	j	ra

	.end	cacheTx49ICInvalidateAll

/*******************************************************************************
*
* cacheTx49ICInvalidate - invalidate Tx49 instruction cache locations
*
* RETURNS: N/A
*

* void cacheTx49ICInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx49ICInvalidate
FUNC_LABEL(cacheTx49ICInvalidate)
	lw	a2,cacheTx49ICacheSize
	blez	a2, 99f
	lw	a3,cacheTx49ICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
	
99:	j	ra
	.end	cacheTx49ICInvalidate


#ifdef IS_KSEGM
/******************************************************************************
*
* cacheTx49VirtPageFlush - flush one page of virtual addresses from caches
*
* Change ASID, flush the appropriate cache lines from the D- and I-cache,
* and restore the original ASID.
*
* CAVEAT: This routine and the routines it calls MAY be running to clear
* cache for an ASID which is only partially mapped by the MMU. For that
* reason, the caller may want to lock interrupts.
*
* RETURNS: N/A
*
* void cacheTx49VirtPageFlush (UINT asid, void *vAddr, UINT pageSize);
*/
	.ent	cacheTx49VirtPageFlush
FUNC_LABEL(cacheTx49VirtPageFlush)
	/* Save parameters */

	move	t4,a0			/* ASID to flush */
	move	t0,a1			/* beginning VA */
	move	t1,a2			/* length */

	/*
	 * When we change ASIDs, our stack might get unmapped,
	 * so use the stack now to free up some registers for use:
	 *	t0 - virtual base address of page to flush
	 *	t1 - page size
	 *	t2 - original SR
	 *	t3 - original ASID
	 *	t4 - ASID to flush
	 */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ	
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/* change the current ASID to context where page is mapped */

	mfc0	t3, C0_TLBHI		/* read current TLBHI */
	HAZARD_CP_READ
	and	t3, 0xff		/* extract ASID field */
	beq	t3, t4, 0f		/* branch if no need to change */
	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */	
	HAZARD_TLB
0:
	/* clear the virtual addresses from D- and I-caches */
	
	lw	a2,cacheTx49DCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */

	move	a0, t0
	move	a1, t1
	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:
	lw	a2,cacheTx49ICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */

	move	a0,t0
	move	a1,t1
	lw	a3,cacheTx49ICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:	
	/* restore the original ASID */

	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */	
	HAZARD_TLB

	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheTx49VirtPageFlush

/******************************************************************************
*
* cacheTx49Sync - sync region of memory through all caches
*
* RETURNS: N/A
*
* void cacheTx49Sync (void *vAddr, UINT pageSize);
*/
	.ent	cacheTx49Sync
FUNC_LABEL(cacheTx49Sync)
	/* Save parameters */

	move	t0,a0			/* beginning VA */
	move	t1,a1			/* length */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/*
	 * starting with primary caches, push the memory
	 * block out completely
	 */

	sync

	lw	a2,cacheTx49ICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */

	move	a0,t0
	move	a1,t1
	lw	a3,cacheTx49ICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:
	lw	a2,cacheTx49DCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */

	move	a0, t0
	move	a1, t1
	lw	a3,cacheTx49DCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:	
	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheTx49Sync
#endif /* IS_KSEGM */