cacher7kalib.s

VxWorks BSP框架源代码包含头文件和驱动

*
* cacheR7kL2Disable - Disable the L2 cache
*
* RETURNS: N/A
*
* void cacheR7kL2Disable (void)
*/
	.ent	cacheR7kL2Disable
FUNC_LABEL(cacheR7kL2Disable)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check if L2 cache already enabled */
	mfc0	t0,C0_CONFIG
        HAZARD_CP_READ
	and	t1,t0,CFG_SE
	beq	t1,zero,99f

	/* Check if L2 cache sizes set to zero */
	lw	a2,cacheR7kSCacheSize
	blez	a2,99f

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_CP_WRITE

	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/*
	 * Invalidate primary data cache
	 * Data will be flushed to next cache layer
	 */
	lw	a3,cacheR7kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

1:

	/* Writeback-Invalidate secondary cache */
	li	a0,K0BASE
	lw	a1,cacheR7kSCacheSize
	move	a2,a1
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)

	/* push L2 cache completely out to memory */
#ifndef MACRO_SYNC
	sync
#endif

	/* disable the L2 cache */
	and	t1,t0,~CFG_SE
	mtc0	t1,C0_CONFIG
        HAZARD_CP_WRITE

	/* invalidate L2 cache tags */
	mtc0	zero,C0_TAGLO
	mtc0	zero,C0_TAGHI
        HAZARD_CACHE_TAG

	li	a0,K0BASE
	lw	a2,cacheR7kSCacheSize
	lw	a3,cacheR7kSCacheLineSize
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)

	mtc0	t2,C0_SR		/* restore interrupts */
99:	
	j	ra
	.end	cacheR7kL2Disable


/******************************************************************************
*
* cacheR7kL3Enable - enable the L3 cache
*
* RETURNS: N/A
*
* void cacheR7kL3Enable (void)
*/
	.ent	cacheR7kL3Enable
FUNC_LABEL(cacheR7kL3Enable)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check if L3 cache already enabled */
	mfc0	t0,C0_CONFIG
        HAZARD_CP_READ
	and	t1,t0,CFG_TE
	bnez	t1,99f

	/* Check if L3 cache not present or sizes set to zero */
	and	t1,t0,CFG_TC
	bnez	t1,99f
	lw	a2,cacheR7kTCacheSize
	blez	a2,99f

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_INTERRUPT

	sync

	/* invalidate L3 cache tags */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

#ifndef MACRO_SYNC
	sync
#endif

	/* enable the L3 cache */
	or	t1,t0,CFG_TE
	mtc0	t1,C0_CONFIG
        HAZARD_CP_WRITE
	sync

	mtc0	t2,C0_SR		/* restore interrupts */
99:	
	j	ra
	.end	cacheR7kL3Enable

/******************************************************************************
*
* cacheR7kL3Disable - Disable the L3 cache
*
* RETURNS: N/A
*
* void cacheR7kL2Disable (void)
*/
	.ent	cacheR7kL3Disable
FUNC_LABEL(cacheR7kL3Disable)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check if L3 cache already enabled */
	mfc0	t0,C0_CONFIG
        HAZARD_CP_READ
	and	t1,t0,CFG_TE
	beqz	t1,99f

	/* Check if L3 cache sizes set to zero */
	lw	a2,cacheR7kTCacheSize
	blez	a2,99f

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_INTERRUPT

	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/*
	 * Invalidate primary data cache
	 * Data will be flushed to next cache layer
	 */
	lw	a3,cacheR7kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

1:

	/* Check for secondary data cache */
	and	t1,t0,CFG_SC
	bnez	t1,1f
	and	t1,t0,CFG_SE
	beqz	t1,1f
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Writeback-Invalidate secondary cache */
	li	a0,K0BASE
	lw	a1,cacheR7kSCacheSize
	move	a2,a1
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)

1:
	/* push L1 & L2 cache completely out to memory */
#ifndef MACRO_SYNC
	sync
#endif

	/* L3 cache is writethrough, so no writeback needed */

	/* disable the L3 cache */
	and	t1,t0,~CFG_TE
	mtc0	t1,C0_CONFIG
        HAZARD_CP_WRITE

	/* invalidate L3 cache tags */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

	mtc0	t2,C0_SR		/* restore interrupts */
99:	
	j	ra
	.end	cacheR7kL3Disable

#ifdef IS_KSEGM
/******************************************************************************
*
* cacheR7kVirtPageFlush - flush one page of virtual addresses from caches
*
* Change ASID, flush the appropriate cache lines from the D- and I-cache,
* and restore the original ASID.
*
* CAVEAT: This routine and the routines it calls MAY be running to clear
* cache for an ASID which is only partially mapped by the MMU. For that
* reason, the caller may want to lock interrupts.
*
* RETURNS: N/A
*
* void cacheR7kVirtPageFlush (UINT asid, void *vAddr, UINT pageSize);
*/
	.ent	cacheR7kVirtPageFlush
FUNC_LABEL(cacheR7kVirtPageFlush)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t4,a0			/* ASID to flush */
	move	t0,a1			/* beginning VA */
	move	t1,a2			/* length */

	/*
	 * When we change ASIDs, our stack might get unmapped,
	 * so use the stack now to free up some registers for use:
	 *	t0 - virtual base address of page to flush
	 *	t1 - page size
	 *	t2 - original SR
	 *	t3 - original ASID
	 *	t4 - ASID to flush
	 */

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_INTERRUPT

	sync

	/* change the current ASID to context where page is mapped */

	mfc0	t3, C0_TLBHI		/* read current TLBHI */
        HAZARD_CP_READ
	and	t3, 0xff		/* extract ASID field */
	beq	t3, t4, 0f		/* branch if no need to change */
	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */	
        HAZARD_CP_WRITE
0:
	/* clear the virtual addresses from D- and I-caches */
	
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:
	lw	a2,cacheR7kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:	
	/* check for secondary cache */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* check for secondary cache ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SE
	beq	t9,zero,1f
	
	/* Flush-invalidate secondary cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)	
1:
	/* restore the original ASID */

	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */	
	mtc0	t2, C0_SR		/* restore interrupts */
        HAZARD_CP_WRITE
	
	j	ra
	.end	cacheR7kVirtPageFlush
	
/******************************************************************************
*
* cacheR7kSync - sync region of memory through all caches
*
* RETURNS: N/A
*
* void cacheR7kSync (void *vAddr, UINT pageSize);
*/
	.ent	cacheR7kSync
FUNC_LABEL(cacheR7kSync)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t0,a0			/* beginning VA */
	move	t1,a1			/* length */

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_INTERRUPT

	/*
	 * starting with primary caches, push the memory
	 * block out completely
	 */
	sync

	lw	a2,cacheR7kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:	
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* check for secondary cache ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SE
	beq	t9,zero,1f

	/* Flush-invalidate secondary cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)	
1:
	/* Check for tertiary cache */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */
	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)	
1:
	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheR7kSync
#endif