cacher7kalib.s

VxWorks BSP框架源代码包含头文件和驱动

	/* Save parameters */
	move	t0,a0
	move	t1,a1

	/* check for secondary cache present and ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/*
	 * Note: if secondary cache is present and enabled, a flush of
	 * secondary cache addresses automatically flushes corresponding
	 * primary data cache addresses.
	 */

	/* Flush-invalidate secondary data cache */
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)

	b	3f

1:
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)

3:
	/* check for T-cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_TC		/* TC=0 if T-cache is present */
	bnez	t9,1f			/* branch if T-cache is not present */
	and	t9,t8,CFG_TE
	beqz	t9,1f			/* branch if T-cache is not enabled */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */

	/*
	 * ENTIRE cache must be cleared, because all T-cache operations
	 * on the R7k are Indexed (no support for virtual addresses).
	 */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

1:
	j	ra
	.end	cacheR7kDCFlushInvalidate


/*******************************************************************************
*
* cacheR7kICInvalidateAll - invalidate entire R7000 instruction cache
*
* RETURNS: N/A
*

* void cacheR7kICInvalidateAll (void)

*/
	.ent	cacheR7kICInvalidateAll
FUNC_LABEL(cacheR7kICInvalidateAll)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check for primary instruction cache */
	lw	a2,cacheR7kICacheSize
	blez	a2,1f

	/* Invalidate primary instruction cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kICacheLineSize
	icacheop(a0,a1,a2,a3,Index_Invalidate_I)

1:
#if DESCEND_ICACHE_INVALIDATE_HIERARCHY
	/* Check for secondary cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	mtc0	zero,C0_TAGLO
	mtc0	zero,C0_TAGHI
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)

1:
	/* Check for T cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_TC		/* TC=0 if T-cache is present */
	bnez	t9,1f			/* branch if T-cache is not present */
	and	t9,t8,CFG_TE
	beqz	t9,1f			/* branch if T-cache is not enabled */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */

	/*
	 * ENTIRE cache must be cleared, because all T-cache operations
	 * on the R7k are Indexed (no support for virtual addresses).
	 */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

#endif

1:

	j	ra
	.end	cacheR7kICInvalidateAll

/*******************************************************************************
*
* cacheR7kICInvalidate - invalidate R7000 instruction cache locations
*
* RETURNS: N/A
*

* void cacheR7kICInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR7kICInvalidate
FUNC_LABEL(cacheR7kICInvalidate)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t0,a0
	move	t1,a1

	/* Check for primary instruction cache */
	lw	a2,cacheR7kICacheSize
	blez	a2,1f

	/* Invalidate primary instruction cache */
	lw	a3,cacheR7kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)

1:

	j	ra
	.end	cacheR7kICInvalidate

/******************************************************************************
*
* cacheR7kPTextUpdateAll - text update for entire cache.
*
* RETURNS: N/A
*

* void cacheR7kPTextUpdateAll (void)

*/
	.ent	cacheR7kPTextUpdateAll
FUNC_LABEL(cacheR7kPTextUpdateAll)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* check for secondary cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
#ifndef MACRO_SYNC
	sync
#endif
1:	
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Invalidate primary data cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a2,cacheR7kDCacheSize
	lw	a3,cacheR7kDCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
#ifndef MACRO_SYNC
	sync
#endif
1:
#ifndef MACRO_SYNC
	sync
#endif
	
	/* Check for primary instruction cache */
	lw	a2,cacheR7kICacheSize
	blez	a2,1f

	/* Invalidate primary instruction cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kICacheLineSize
	icacheop(a0,a1,a2,a3,Index_Invalidate_I)
#ifndef MACRO_SYNC
	sync
#endif
1:
	j	ra
	.end	cacheR7kPTextUpdateAll

/******************************************************************************
*
* cacheR7kRomTextUpdate - text update for entire cache.
*
* RETURNS: N/A
*

* void cacheR7kRomTextUpdate (void)

*/
	.ent	cacheR7kRomTextUpdate
FUNC_LABEL(cacheR7kRomTextUpdate)
	SETFRAME(cacheR7kRomTextUpdate, 0)
	subu	sp, FRAMESZ(cacheR7kRomTextUpdate)
	SW	ra, FRAMERA(cacheR7kRomTextUpdate)(sp)	/* save return address */
	sw	a0, cacheR7kICacheSize
	sw	a1, cacheR7kICacheLineSize
	sw	a2, cacheR7kDCacheSize
	sw	a3, cacheR7kDCacheLineSize
	LW	t0, FRAMEA(cacheR7kRomTextUpdate,4)(sp)
	sw	t0, cacheR7kSCacheSize
	LW	t0, FRAMEA(cacheR7kRomTextUpdate,5)(sp)
	sw	t0, cacheR7kSCacheLineSize
	LW	t0, FRAMEA(cacheR7kRomTextUpdate,6)(sp)
	sw	t0, cacheR7kTCacheSize
	LW	t0, FRAMEA(cacheR7kRomTextUpdate,7)(sp)
	sw	t0, cacheR7kTCacheLineSize
	jal	cacheR7kPTextUpdateAll
	LW	ra, FRAMERA(cacheR7kRomTextUpdate)(sp)	/* restore return address */
	addu	sp, FRAMESZ(cacheR7kRomTextUpdate)
	j	ra
	.end	cacheR7kRomTextUpdate
	
/******************************************************************************
*
* cacheR7kPTextUpdate - text update primary caches
*
* RETURNS: N/A
*

* void cacheR7kPTextUpdate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR7kPTextUpdate
FUNC_LABEL(cacheR7kPTextUpdate)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t0,a0
	move	t1,a1

	/* check for secondary cache present and ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,2f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,2f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,2f
	
	/*
	 * Note: if secondary cache is present and enabled, a flush of
	 * secondary cache addresses automatically flushes corresponding
	 * primary data cache addresses.
	 */
	
	/* Flush-invalidate secondary data cache */
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
#ifndef MACRO_SYNC
	sync
#endif
	b	1f		/* no need to flush/invalidate primary data cache */
2:	

	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
#ifndef MACRO_SYNC
	sync
#endif
1:

	/* Check for primary instruction cache */
	lw	a2,cacheR7kICacheSize
	blez	a2,1f

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR7kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
#ifndef MACRO_SYNC
	sync
#endif
1:
	j	ra
	.end	cacheR7kPTextUpdate


/******************************************************************************
*
* cacheR7kL2Enable - enable the L2 cache
*
* RETURNS: N/A
*
* void cacheR7kL2Enable (void)
*/
	.ent	cacheR7kL2Enable
FUNC_LABEL(cacheR7kL2Enable)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check if L2 cache already enabled */
	mfc0	t0,C0_CONFIG
        HAZARD_CP_READ
	and	t1,t0,CFG_SE
	bnez	t1,99f

	/* Check if L2 cache not present or sizes set to zero */
	and	t1,t0,CFG_SC
	bnez	t1,99f
	lw	a2,cacheR7kSCacheSize
	blez	a2,99f

	/* lock interrupts */

	mfc0	t2,C0_SR
        HAZARD_CP_READ
	li	t3,~SR_INT_ENABLE
	and	t3,t2
	mtc0	t3,C0_SR
        HAZARD_INTERRUPT

	sync

	/* invalidate L2 cache tags */
	mtc0	zero,C0_TAGLO
	mtc0	zero,C0_TAGHI
	HAZARD_CP_WRITE

	li	a0,K0BASE
	lw	a2,cacheR7kSCacheSize
	lw	a3,cacheR7kSCacheLineSize
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)

	/* enable the L2 cache */
	or	t1,t0,CFG_SE
	mtc0	t1,C0_CONFIG
        HAZARD_CP_WRITE

	mtc0	t2,C0_SR		/* restore interrupts */
99:	
	j	ra
	.end	cacheR7kL2Enable

/******************************************************************************