cacher7kalib.s

VxWorks BSP框架源代码包含头文件和驱动

#endif /* INVALIDATE_T_MODE */

0:
3:	
	sync
	mtc0	t8,C0_CONFIG
	mtc0	v0,C0_SR
        HAZARD_CP_WRITE
	j	ra
	.end	cacheR7kReset

/*******************************************************************************
*
* cacheR7kDCFlushAll - flush entire R7000 data cache
*
* There is no way to do *only* a data cache flush, so we do a flush-invalidate.
* 
* Tertiary cache is Writethrough, so no Writeback is necessary
*
* RETURNS: N/A
*

* void cacheR7kDCFlushAll (void)

*/
	.ent	cacheR7kDCFlushAll
FUNC_LABEL(cacheR7kDCFlushAll)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/*
	 * Invalidate primary data cache
	 * Data will be flushed to next cache layer
	 */
	lw	a3,cacheR7kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

1:
	/* check for secondary cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)

	/* no need to flush tertiary cache: it's write through and therefore always
	 * consistent with main memory */
1:
#ifndef MACRO_SYNC
	sync
#endif
	j	ra

	.end	cacheR7kDCFlushAll

/*******************************************************************************
*
* cacheR7kDCFlush - flush R7000 data cache locations
*
* There is no way to do *only* a data cache flush, so we do a flush-invalidate.
*
* Tertiary cache is Writethrough, so no Writeback is necessary
*
* RETURNS: N/A
*
*
* void cacheR7kDCFlush
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR7kDCFlush
FUNC_LABEL(cacheR7kDCFlush)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t0,a0
	move	t1,a1

	/* check for secondary cache present and ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,2f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,2f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,2f

	/*
	 * Note: if secondary cache is present and enabled, a flush of
	 * secondary cache addresses automatically flushes corresponding
	 * primary data cache addresses.
	 */

	/* Flush-invalidate secondary data cache */
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)

	b	1f

2:
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)

	/* no need to flush tertiary cache: it's write through and therefore always
	 * consistent with main memory */
1:
#ifndef MACRO_SYNC
	sync
#endif
	j	ra
	.end	cacheR7kDCFlush


/*******************************************************************************
*
* cacheR7kDCInvalidateAll - flush entire R7000 data cache
*
* There is no Index_Invalidate_D or Index_Invalidate_SD function, so we 
* do an Index_Writeback_Inv_{D,SD} instead.
*
* RETURNS: N/A
*

* void cacheR7kDCInvalidateAll (void)

*/
	.ent	cacheR7kDCInvalidateAll
FUNC_LABEL(cacheR7kDCInvalidateAll)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/*
	 * Invalidate primary data cache
	 * Data will be flushed to next cache layer
	 */
	lw	a3,cacheR7kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

1:
	/* check for secondary cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)

1:
	/* check for T-cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_TC		/* TC=0 if T-cache is present */
	bnez	t9,1f			/* branch if T-cache is not present */
	and	t9,t8,CFG_TE
	beqz	t9,1f			/* branch if T-cache is not enabled */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

1:
	j	ra

	.end	cacheR7kDCInvalidateAll

/*******************************************************************************
*
* cacheR7kDCInvalidate - flush R7000 data cache locations
*
* RETURNS: N/A
*

* void cacheR7kDCInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR7kDCInvalidate
FUNC_LABEL(cacheR7kDCInvalidate)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Save parameters */
	move	t0,a0
	move	t1,a1

	/* check for secondary cache present and ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/*
	 * Note: if secondary cache is present and enabled, invalidating
	 * secondary cache addresses automatically invalidates corresponding
	 * primary data cache addresses.
	 */

	/* Invalidate secondary data cache */
	lw	a3,cacheR7kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)

	b	3f

1:
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/* Invalidate primary data cache */
	lw	a3,cacheR7kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)

3:
	/* check for T-cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_TC		/* TC=0 if T-cache is present */
	bnez	t9,1f			/* branch if T-cache is not present */
	and	t9,t8,CFG_TE
	beqz	t9,1f			/* branch if T-cache is not enabled */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */

	/*
	 * ENTIRE cache must be cleared, because all T-cache operations
	 * on the R7k are Indexed (no support for virtual addresses).
	 */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

1:
	j	ra
	.end	cacheR7kDCInvalidate

/*******************************************************************************
*
* cacheR7kDCFlushInvalidateAll - flush entire R7000 data cache
*
* Tertiary cache is Writethrough, so no Writeback is necessary
*
* RETURNS: N/A
*

* void cacheR7kDCFlushInvalidateAll (void)

*/
	.ent	cacheR7kDCFlushInvalidateAll
FUNC_LABEL(cacheR7kDCFlushInvalidateAll)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	
	/* Check for primary data cache */
	lw	a2,cacheR7kDCacheSize
	blez	a2,1f

	/*
	 * Invalidate primary data cache
	 * Data will be flushed to next cache layer
	 */
	lw	a3,cacheR7kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

1:
	/* check for secondary cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_SC		/* SC=0 if S-cache is present */
	bnez	t9,1f			/* branch if S-cache is not present */
	and	t9,t8,CFG_SE
	beqz	t9,1f			/* branch if S-cache is not enabled */
	lw	a2,cacheR7kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)

1:
	/* check for T-cache present & ENABLED, skip if not */
	mfc0	t8,C0_CONFIG
        HAZARD_CP_READ
	and	t9,t8,CFG_TC		/* TC=0 if T-cache is present */
	bnez	t9,1f			/* branch if T-cache is not present */
	and	t9,t8,CFG_TE
	beqz	t9,1f			/* branch if T-cache is not enabled */
	lw	a2,cacheR7kTCacheSize
	blez	a2,1f

	/* Invalidate tertiary cache */

#if (INVALIDATE_T_MODE == INVALIDATE_T_MODE_FLASH)

	li	a0,K0BASE
	cache	Flash_Invalidate_T,0(a0)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_PAGE)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	sll	a3,PAGE_SHIFT
	icacheop(a0,a1,a2,a3,Page_Invalidate_T)

#elif (INVALIDATE_T_MODE == INVALIDATE_T_MODE_INDEX)

	mtc0	zero,C0_TAGLO  /* Set invalid state in TagLo register */
	mtc0	zero,C0_TAGHI  /* Set invalid state in TagHi register */
	HAZARD_CACHE_TAG
	li	a0,K0BASE
	move	a1,a2
	lw	a3,cacheR7kTCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_T)

#else

#error "INVALIDATE_T_MODE value incorrect"

#endif /* INVALIDATE_T_MODE */

1:
	j	ra

	.end	cacheR7kDCFlushInvalidateAll

/*******************************************************************************
*
* cacheR7kDCFlushInvalidate - flush R7000 data cache locations
*
* RETURNS: N/A
*

* void cacheR7kDCFlushInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR7kDCFlushInvalidate
FUNC_LABEL(cacheR7kDCFlushInvalidate)
	/* run from kseg1 */
	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1: