cachesb1alib.s

VxWorks BSP框架源代码包含头文件和驱动

/* cacheSb1ALib.s: Assembly routines for Broadcom SB-1 Core (L1 and L2) Caches */

/* Copyright 2002 Wind River Systems, Inc. */
        .data
        .globl  copyright_wind_river

/* 
*  Copyright 2000,2001
*  Broadcom Corporation. All rights reserved.
* 
*  This software is furnished under license to Wind River Systems, Inc.
*  and may be used only in accordance with the terms and conditions 
*  of this license.  No title or ownership is transferred hereby.
*/

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01e,24jun02,pgh  Add the L2 cache code from the BSP.
01d,18jan02,agf  add explicit align directive to data section(s)
01c,04dec01,agf  add Broadcom copyright notice
01b,03dec01,agf  remove unnecessry assembler directives
01a,14nov01,agf  created.
*/

/*
DESCRIPTION
This library contains Broadcom Sb1 cache set-up and invalidation routines
written in assembly language.  The Sb1 utilizes a variable-size
instruction and data cache that operates in write-back (only) mode.  At 
this time, this code assumes 32-byte cache lines.  See also the manual 
entry for cacheSb1Lib.

This library contains Broadcom BCM1250 L2 cache set-up and invalidation 
routines written in assembly language. It relies on registers only since DRAM 
may not be active yet.  This code assumes the line size is always 32 bytes.

For general information about caching, see the manual entry for cacheLib.

INCLUDE FILES: cacheLib.h

SEE ALSO: cacheSb1Lib, cacheLib
*/


#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"

#include "drv/multi/bcm1250Lib.h"


	/* constants */

#define L1CACHE_NUMWAYS     4
#define L1CACHE_NUMIDX      256
#define L1CACHE_LINESIZE    32
#define L1CACHE_IDXHIGH     (L1CACHE_LINESIZE*L1CACHE_NUMWAYS*L1CACHE_NUMIDX)

#define L2CACHE_LINESIZE    32
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS        4


    /* macros */

#define PHYS_TO_XKSEG_CACHED(x)   (0xa100000000000000|(x))
#define PHYS_TO_XKSEG_UNCACHED(x) (0x9000000000000000|(x))

/* in archMips.h these macros are not assembler friendly, so fix for here */

#undef  PHYS_TO_K0
#define PHYS_TO_K0(x)   (K0BASE | (x))
#undef  PHYS_TO_K1
#define PHYS_TO_K1(x)   (K1BASE | (x))


	/* globals */

	.text

	.globl	GTEXT(cacheSb1Reset)
	.globl	GTEXT(cacheSb1DCFlushInvalidateAll)
	.globl	GTEXT(cacheSb1DCFlushInvalidateLines)
	.globl	GTEXT(cacheSb1ICInvalidateAll)
	.globl	GTEXT(cacheSb1ICInvalidateLines)
	.globl	GTEXT(sb1CacheExcVec)

	.globl	GDATA(cacheSb1ICacheSize)
	.globl	GDATA(cacheSb1DCacheSize)

	.globl	GDATA(cacheSb1ICacheLineSize)
	.globl	GDATA(cacheSb1DCacheLineSize)

        .data
	.align	4
cacheSb1ICacheSize:
        .word   0                       /* instruction cache size */
cacheSb1DCacheSize:
        .word   0                       /* data cache size */
cacheSb1ICacheLineSize:
        .word   0                       /* instruction cache line size */
cacheSb1DCacheLineSize:
        .word   0                       /* data cache line size */


	.text

/******************************************************************************
*
* cacheSb1Reset - low level initialisation of the Sb1 L1 caches
*
* This routine initialises the Sb1 L1 caches to ensure that all entries are
* marked invalid.  It must be called by the ROM before any cached locations
* are used to prevent the possibility of uninitialized data being written to
* memory.
*
* Arguments
*       t0 - size of instruction cache in bytes
*       t1 - size of instruction cache line in bytes
*       t2 - size of data cache in bytes
*       t3 - size of data cache line in bytes
*
* RETURNS: N/A
*

* void cacheSb1Reset

*/
        .ent    cacheSb1Reset
FUNC_LABEL(cacheSb1Reset)
        /* disable all i/u and cache exceptions */
        mfc0    v0,C0_SR
        HAZARD_CP_READ
        and     v1,v0,SR_BEV
        or      v1,v0,SR_DE
        mtc0    v1,C0_SR

        /* set tag & ecc to 0 */
        mtc0    zero,C0_TAGLO
        mtc0    zero,C0_TAGHI
        mtc0    zero,C0_ECC
        HAZARD_CP_WRITE

        /* Initialize the instruction cache */
        li      t2,K1BASE
        li      t3,L1CACHE_IDXHIGH

        add     t0,t2,t3
        .align  4
1:      cache   Index_Store_Tag_I, 0(t2)
        addu    t2,L1CACHE_LINESIZE
        bne     t0,t2,1b

        /* dmtc0   zero,C0_TAGLO,2 */
        /* dmtc0   zero,C0_TAGHI,2 */
        .word   0x40a0e002
        .word   0x40a0e802

        li      t2,K1BASE
        add     t0,t2,t3
        .align  4
1:      cache   Index_Store_Tag_D, 0(t2)
        addu    t2,L1CACHE_LINESIZE
        bne     t0,t2,1b

        mtc0    v0,C0_SR
        HAZARD_CP_WRITE
        j       ra
        .end    cacheSb1Reset


/*******************************************************************************
*
* cacheSb1DCFlushInvalidateAll - flush entire Sb1 data cache
*
* RETURNS: N/A
*

* void cacheSb1DCFlushInvalidateAll (void)

*/
        .ent    cacheSb1DCFlushInvalidateAll
FUNC_LABEL(cacheSb1DCFlushInvalidateAll)

	li	a0, K0BASE
	lw	t1, cacheSb1DCacheSize
	.set noreorder
1:	beqz	t1, 2f
	subu	t1, t1, 8
	cache	Index_Writeback_Inv_D, 0*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 1*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 2*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 3*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 4*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 5*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 6*L1CACHE_LINESIZE(a0)
	cache	Index_Writeback_Inv_D, 7*L1CACHE_LINESIZE(a0)
	b	1b
	addu	a0, a0, 8*L1CACHE_LINESIZE
	.set reorder
2:
	j	ra
	.end	cacheSb1DCFlushInvalidateAll


/*******************************************************************************
*
* cacheSb1DCFlushInvalidateLines - flush selected  Sb1 data cache lines
*
* RETURNS: N/A
*

* void cacheSb1DCFlushInvalidateLines (unsigned int addr, unsigned int lines)

*/
        .ent    cacheSb1DCFlushInvalidateLines
FUNC_LABEL(cacheSb1DCFlushInvalidateLines)

	.set noreorder
1:
	subu	a1, a1, 1
	cache	Hit_Writeback_Inv_D, 0(a0)
	bnez	a1, 1b
	addu	a0, a0, L1CACHE_LINESIZE
	.set reorder

	j	ra
	.end	cacheSb1DCFlushInvalidateLines



/*******************************************************************************
*
* cacheSb1ICFlushInvalidateAll - flush entire Sb1 instruction cache
*
* RETURNS: N/A
*

* void cacheSb1ICFlushInvalidateAll (void)

*/
        .ent    cacheSb1ICInvalidateAll
FUNC_LABEL(cacheSb1ICInvalidateAll)

	li	a0, K0BASE
	lw	t1, cacheSb1ICacheSize
	.set noreorder
1:	beqz	t1, 2f
	subu	t1, t1, 8
	cache	Index_Invalidate_I, 0*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 1*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 2*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 3*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 4*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 5*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 6*L1CACHE_LINESIZE(a0)
	cache	Index_Invalidate_I, 7*L1CACHE_LINESIZE(a0)
	b	1b
	addu	a0, a0, 8*L1CACHE_LINESIZE
	.set reorder
2:
	j	ra
	.end	cacheSb1ICInvalidateAll


/*******************************************************************************
*
* cacheSb1DCFlushInvalidateLines - flush selected Sb1 instruction cache lines
*
* RETURNS: N/A
*

* void cacheSb1ICFlushInvalidateLines (unsigned int addr, unsigned int lines)

*/
        .ent    cacheSb1ICInvalidateLines
FUNC_LABEL(cacheSb1ICInvalidateLines)
	.set noreorder
1:
	subu	a1, a1, 1
	cache	Hit_Invalidate_I, 0(a0)
	bnez	a1, 1b
	addu	a0, a0, L1CACHE_LINESIZE
	.set reorder

	j	ra