📄 fppalib.s
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and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */5: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ and t3, t0, GENERAL_OPCODE_MASK /* get branch opcode */ beq t3, BNE_INSTR,1f bne t3, BNEL_INSTR,6f /* are we bne/bnel instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ and t2, t0, RT_MASK /* look at RT only */ srl t2, (RT_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RT register */ move t5, v0 /* store value in t5 */ beq t4, t5, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */6: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ and t3, t0, GENERAL_OPCODE_MASK /* get branch opcode */ beq t3, BLEZ_INSTR,1f bne t3, BLEZL_INSTR,7f /* are we blez/blezl instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ bgtz t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */7: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ or t1, t0, REGIMM /* turn on REGIMM bits */ and t2, t1, RS_MASK /* mask RS bits */ beq t2, BGEZ_INSTR, 1f bne t2, BGEZL_INSTR, 8f /* are we bgez/bgezl instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ bltz t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */8: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ or t1, t0, REGIMM /* turn on REGIMM bits */ and t2, t1, RS_MASK /* mask RS bits */ beq t2, BLTZ_INSTR, 1f bne t2, BLTZL_INSTR, 9f /* are we bltz/bltzl instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ bgez t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */9: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ and t3, t0, GENERAL_OPCODE_MASK /* get branch opcode */ beq t3, BGTZ_INSTR, 1f bne t3, BGTZL_INSTR, 10f /* are we bgtz/bgtzl instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ blez t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */10: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ and t1, t0, ~CC_MASK /* mask off bits 18-20 */ beq t1, BC1F_INSTR, 1f bne t1, BC1FL_INSTR, 11f /* are we bc1f/bc1fl instr */1: and t4, a2, CP1_VALUE /* is fpa true */ bne zero, t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */11: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ and t1, t0, ~CC_MASK /* mask off bits 18-20 */ beq t1, BC1T_INSTR, 1f bne t1, BC1TL_INSTR, 12f /* are we bc1t/bc1tl instr */1: and t4, a2, CP1_VALUE /* is fpa true */ beq zero, t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */12: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ or t1, t0, REGIMM /* turn on REGIMM bits */ and t2, t1, RS_MASK /* mask RS bits */ beq t2, BLTZAL_INSTR, 1f bne t2, BLTZALL_INSTR, 13f /* are we bltzal/bltzall instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ bgez t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addu t2, t1, 8 /* increment epc for ra */ sw t2, E_STK_RA(a0) /* replace ra */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */13: and t0, a1, (OFFSET16_MASK << 16) /* mask high 16 bits */ or t1, t0, REGIMM /* turn on REGIMM bits */ and t2, t1, RS_MASK /* mask RS bits */ beq t2, BGEZAL_INSTR,1f bne t2, BGEZALL_INSTR,14f /* are we bgtzal/bgtzall instr */1: and t2, t0, RS_MASK /* look at RS only */ srl t2, (RS_POS - 2) lw t2, regFetchIndexTbl(t2) /* get routine address */ jalr t7, t2 /* read RS register */ move t4, v0 /* store value in t4 */ bltz t4, 15f /* don't take branch */ and a1, OFFSET16_MASK /* look at ls 16 bits */ sll a1, IMMEDIATE_POS /* sign extend */ sra a1, IMMEDIATE_POS - 2 lw t1, E_STK_EPC(a0) /* grab epc */ addu t2, t1, 8 /* increment epc for ra */ sw t2, E_STK_RA(a0) /* replace ra */ addiu t1, t1, 4 /* calculate BD slot addr */ addu v0, t1, a1 /* calculate new epc */ j ra /* return */#endif /* !SOFT_FLOAT */14: /* it wasn't a branch that we recognised! */ li v0, 1 /* give up */15: j ra /* return to caller */ .end fppEmulateBranch/********************************************************************************* regFetchTable - returns the contents of a given register** This routine has 32 entry points, one for each r3k general purpose* register. The user interface is to jal to the register offset of* regFetchIndexTbl, and expect results in v0. The return address register* t7 is uses so we do not have to set up a stack frame.** RETURNS: contents of given register** NOMANUAL - not really a routine but a jump table*/ .ent regFetchTableregFetchTable:reg0: move v0, zero j t7reg1: LW v0,E_STK_AT(a0) j t7reg2: LW v0,E_STK_V0(a0) j t7reg3: LW v0,E_STK_V1(a0) j t7reg4: LW v0,E_STK_A0(a0) j t7reg5: LW v0,E_STK_A1(a0) j t7reg6: LW v0,E_STK_A2(a0) j t7reg7: LW v0,E_STK_A3(a0) j t7reg8: LW v0,E_STK_T0(a0) j t7reg9: LW v0,E_STK_T1(a0) j t7reg10: LW v0,E_STK_T2(a0) j t7reg11: LW v0,E_STK_T3(a0) j t7reg12: LW v0,E_STK_T4(a0) j t7reg13: LW v0,E_STK_T5(a0) j t7reg14: LW v0,E_STK_T6(a0) j t7reg15: LW v0,E_STK_T7(a0) j t7reg16: LW v0,E_STK_S0(a0) j t7reg17: LW v0,E_STK_S1(a0) j t7reg18: LW v0,E_STK_S2(a0) j t7reg19: LW v0,E_STK_S3(a0) j t7reg20: LW v0,E_STK_S4(a0) j t7reg21: LW v0,E_STK_S5(a0) j t7reg22: LW v0,E_STK_S6(a0) j t7reg23: LW v0,E_STK_S7(a0) j t7reg24: LW v0,E_STK_T8(a0) j t7reg25: LW v0,E_STK_T9(a0) j t7reg26: LW v0,E_STK_K0(a0) j t7reg27: LW v0,E_STK_K1(a0) j t7reg28: LW v0,E_STK_GP(a0) j t7reg29: LW v0,E_STK_SP(a0) j t7reg30: LW v0,E_STK_FP(a0) j t7reg31: LW v0,E_STK_RA(a0) j t7 .end regFetchTable/********************************************************************************* regJumpTable - excecution code for jump instruction execution** This routine contains the local symbols used by regJmpIndexTbl to determine* what action should be taken by certain MIPS instructions. This routine is* not callable by any "C" or assembler routines.** RETURNS: N/A** NOMANUAL - not really a routine but a jump table*/ .ent regJumpTableregJumpTable:jreg0: lw t1,E_STK_ZERO(a0) sw t1,E_STK_EPC(a0) j rajreg1: lw t1,E_STK_AT(a0) sw t1,E_STK_EPC(a0) j rajreg2: lw t1,E_STK_V0(a0) sw t1,E_STK_EPC(a0) j rajreg3: lw t1,E_STK_V1(a0) sw t1,E_STK_EPC(a0) j rajreg4: lw t1,E_STK_A0(a0) sw t1,E_STK_EPC(a0) j rajreg5: lw t1,E_STK_A1(a0) sw t1,E_STK_EPC(a0) j rajreg6: lw t1,E_STK_A2(a0) sw t1,E_STK_EPC(a0) j rajreg7: lw t1,E_STK_A3(a0) sw t1,E_STK_EPC(a0) j rajreg8: lw t1,E_STK_T0(a0) sw t1,E_STK_EPC(a0) j rajreg9: lw t1,E_STK_T1(a0) sw t1,E_STK_EPC(a0) j rajreg10: lw t1,E_STK_T2(a0) sw t1,E_STK_EPC(a0) j rajreg11: lw t1,E_STK_T3(a0) sw t1,E_STK_EPC(a0) j rajreg12: lw t1,E_STK_T4(a0) sw t1,E_STK_EPC(a0) j rajreg13: lw t1,E_STK_T5(a0) sw t1,E_STK_EPC(a0) j rajreg14: lw t1,E_STK_T6(a0) sw t1,E_STK_EPC(a0) j rajreg15: lw t1,E_STK_T7(a0) sw t1,E_STK_EPC(a0) j rajreg16: lw t1,E_STK_S0(a0) sw t1,E_STK_EPC(a0) j rajreg17: lw t1,E_STK_S1(a0) sw t1,E_STK_EPC(a0) j rajreg18: lw t1,E_STK_S2(a0) sw t1,E_STK_EPC(a0) j rajreg19: lw t1,E_STK_S3(a0) sw t1,E_STK_EPC(a0) j rajreg20: lw t1,E_STK_S4(a0) sw t1,E_STK_EPC(a0) j rajreg21: lw t1,E_STK_S5(a0) sw t1,E_STK_EPC(a0) j rajreg22: lw t1,E_STK_S6(a0) sw t1,E_STK_EPC(a0) j rajreg23: lw t1,E_STK_S7(a0) sw t1,E_STK_EPC(a0) j rajreg24: lw t1,E_STK_T8(a0) sw t1,E_STK_EPC(a0) j rajreg25: lw t1,E_STK_T9(a0) sw t1,E_STK_EPC(a0) j rajreg26: lw t1,E_STK_K0(a0) sw t1,E_STK_EPC(a0) j rajreg27: lw t1,E_STK_K1(a0) sw t1,E_STK_EPC(a0) j rajreg28: lw t1,E_STK_GP(a0) sw t1,E_STK_EPC(a0) j rajreg29: lw t1,E_STK_SP(a0) sw t1,E_STK_EPC(a0) j rajreg30: lw t1,E_STK_FP(a0) sw t1,E_STK_EPC(a0) j rajreg31: lw t1,E_STK_RA(a0) sw t1,E_STK_EPC(a0) j ra .end regJumpTable .data .align 4regJmpIndexTbl: .word jreg0 .word jreg1 .word jreg2 .word jreg3 .word jreg4 .word jreg5 .word jreg6 .word jreg7 .word jreg8 .word jreg9 .word jreg10 .word jreg11 .word jreg12 .word jreg13 .word jreg14 .word jreg15 .word jreg16 .word jreg17 .word jreg18 .word jreg19 .word jreg20 .word jreg21 .word jreg22 .word jreg23 .word jreg24 .word jreg25 .word jreg26 .word jreg27 .word jreg28 .word jreg29 .word jreg30 .word jreg31 .data .align 4regFetchIndexTbl: .word reg0 .word reg1 .word reg2 .word reg3 .word reg4 .word reg5 .word reg6 .word reg7 .word reg8 .word reg9 .word reg10 .word reg11 .word reg12 .word reg13 .word reg14 .word reg15 .word reg16 .word reg17 .word reg18 .word reg19 .word reg20 .word reg21 .word reg22 .word reg23 .word reg24 .word reg25 .word reg26 .word reg27 .word reg28 .word reg29 .word reg30 .word reg31⌨️ 快捷键说明
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