cacher10kalib.s

VxWorks BSP框架源代码包含头文件和驱动

	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Invalidate_I)
99:
	j	ra
	.end	cacheR10kRomTextUpdate


/******************************************************************************
*
* cacheR10kDCFlushInvalidateAll - flush entire R10000 data cache
*
* RETURNS: N/A
*

* void cacheR4kDCFlushInvalidateAll (void)

*/
	.ent	cacheR10kDCFlushInvalidateAll
FUNC_LABEL(cacheR10kDCFlushInvalidateAll)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR10kSCacheSize
	blez	a2,1f
	lw	a3,cacheR10kSCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR10kDCacheSize
	lw	a3,cacheR10kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheR10kDCFlushInvalidateAll

	
/******************************************************************************
*
* cacheR10kDCFlushInvalidate - flush R10000 data cache locations
*
* RETURNS: N/A
*

* void cacheR10kDCFlushInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR10kDCFlushInvalidate
FUNC_LABEL(cacheR10kDCFlushInvalidate)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR10kSCacheSize
	blez	a2,1f
	lw	a3,cacheR10kSCacheLineSize
	move	a1,a2
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR10kDCacheSize
	lw	a3,cacheR10kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)

99:	j	ra
	.end	cacheR10kDCFlushInvalidate


/******************************************************************************
*
* cacheR10kICInvalidateAll - invalidate entire R10000 instruction cache
*
* RETURNS: N/A
*

* void cacheR10kICInvalidateAll (void)

*/
	.ent	cacheR10kICInvalidateAll
FUNC_LABEL(cacheR10kICInvalidateAll)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR10kSCacheSize
	blez	a2,1f
	lw	a3,cacheR10kSCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR10kICacheSize
	blez	a2,99f
	lw	a3,cacheR10kICacheLineSize
	li	a0,K0BASE
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Invalidate_I)

99:	j	ra

	.end	cacheR10kICInvalidateAll


/******************************************************************************
*
* cacheR10kICInvalidate - invalidate R10000 instruction cache locations
*
* RETURNS: N/A
*

* void cacheR10kICInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR10kICInvalidate
FUNC_LABEL(cacheR10kICInvalidate)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR10kSCacheSize
	blez	a2,1f
	lw	a3,cacheR10kSCacheLineSize
	move	a1,a2
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR10kICacheSize
	lw	a3,cacheR10kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)

99:	j	ra
	.end	cacheR10kICInvalidate
	
/******************************************************************************
*
* cacheR10kDCLock - lock R10000 data cache locations
*
* Not all architectures support this operation.
*
* RETURNS: N/A
*

* void cacheR10kDCLock
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR10kDCLock
FUNC_LABEL(cacheR10kDCLock)
	lw	a2,cacheR10kDCacheSize
	lw	a3,cacheR10kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Lock_D)
	j	ra
	.end	cacheR10kDCLock

/******************************************************************************
*
* cacheR10kICLock - lock R10000 data cache locations
*
* Not all architectures support this operation.
*
* RETURNS: N/A
*

* void cacheR10kICLock
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR10kICLock
FUNC_LABEL(cacheR10kICLock)
	lw	a2,cacheR10kICacheSize
	lw	a3,cacheR10kICacheLineSize
	vcacheop(a0,a1,a2,a3,Lock_I)
	j	ra
	.end	cacheR10kICLock

/******************************************************************************
*
* cacheR10kVirtPageFlush - flush one page of virtual addresses from caches
*
* Change ASID, flush the appropriate cache lines from the D- and I-cache,
* and restore the original ASID.
*
* CAVEAT: This routine and the routines it calls MAY be running to clear
* cache for an ASID which is only partially mapped by the MMU. For that
* reason, the caller may want to lock interrupts.
*
* RETURNS: N/A
*
* void cacheR10kVirtPageFlush (UINT asid, void *vAddr, UINT pageSize);
*/
	.ent	cacheR10kVirtPageFlush
FUNC_LABEL(cacheR10kVirtPageFlush)
	/* Save parameters */
	move	t4,a0			/* ASID to flush */
	move	t0,a1			/* beginning VA */
	move	t1,a2			/* length */

	/*
	 * When we change ASIDs, our stack might get unmapped,
	 * so use the stack now to free up some registers for use:
	 *	t0 - virtual base address of page to flush
	 *	t1 - page size
	 *	t2 - original SR
	 *	t3 - original ASID
	 *	t4 - ASID to flush
	 */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/* change the current ASID to context where page is mapped */

	mfc0	t3, C0_TLBHI		/* read current TLBHI */
	and	t3, 0xff		/* extract ASID field */
	beq	t3, t4, 0f		/* branch if no need to change */
	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */	
	HAZARD_TLB

0:
	/* clear the virtual addresses from D- and I-caches */
	
	lw	a2,cacheR10kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR10kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:
	lw	a2,cacheR10kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR10kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:	
	/* restore the original ASID */

	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */	
	HAZARD_TLB

	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheR10kVirtPageFlush

	
/******************************************************************************
*
* cacheR10kSync - sync region of memory through all caches
*
* RETURNS: N/A
*
* void cacheR10kSync (void *vAddr, UINT pageSize);
*/
	.ent	cacheR10kSync
FUNC_LABEL(cacheR10kSync)
	/* Save parameters */
	move	t0,a0			/* beginning VA */
	move	t1,a1			/* length */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/*
	 * starting with primary caches, push the memory
	 * block out completely
	 */
	sync

	lw	a2,cacheR10kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR10kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:
	lw	a2,cacheR10kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR10kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:	
	lw	a2,cacheR10kSCacheSize
	blez	a2,1f

	/* Flush-invalidate secondary cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR10kSCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)	
1:
	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheR10kSync