cacher10kalib.s

VxWorks BSP框架源代码包含头文件和驱动

/* cacheR10kALib.s - MIPS R10000 cache management assembly routines */

/* Copyright 1984-2001 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01h,18jan02,agf  add explicit align directive to data section(s)
01g,16nov01,tlc  Reorder icache loops in reset routine.
01g,02aug01,mem  Diab integration
01f,16jul01,ros  add CoE comment
01e,12feb01,tlc  Perform HAZARD review.
01d,03jan01,tlc  Backported from Cirrus.
01c,19jun00,dra  work around 5432 branch bug
01b,24feb00,dra  added defines to aid building under standard product T2.
01a,19jul99,dra  Created this file based in cacheR4kALib.s, 01j.
*/

/*
DESCRIPTION
This library contains MIPS R10000 cache setup, size configuration,
flush and invalidation routines. The MIPS R10000 cache organization 
includes: 1) primary data cache; 2) primary instruction cache; 
3) off-chip secondary cache; The primary caches are 2-way set associative.  
The secondary cache is directly mapped.

For general information about caching, see the manual entry for cacheLib.

INCLUDE FILES: cacheLib.h

SEE ALSO: cacheR10kLib, cacheLib
*/
	
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"

	/* defines */
/*
 * cacheop macro to automate cache operations
 * first some helpers...
 */
#define _mincache(size, maxsize) \
	bltu	size,maxsize,9f ;	\
	move	size,maxsize ;		\
9:

#define _align(minaddr, maxaddr, linesize) \
	.set noat ; \
	subu	AT,linesize,1 ;	\
	not	AT ;			\
	and	minaddr,AT ;		\
	addu	maxaddr,-1 ;		\
	and	maxaddr,AT ;		\
	.set at

/* general operations */
#define doop1(op1) \
	cache	op1,0(a0)	; \
	HAZARD_CACHE
#define doop2(op1, op2) \
	cache	op1,0(a0)	; \
	HAZARD_CACHE		; \
	cache	op2,0(a0)	; \
	HAZARD_CACHE

/* Loop operation for two-way set */ 
/* associative index operations   */
#define doop10(op1) \
	cache	op1,0(a0)	;\
	HAZARD_CACHE		;\
	cache	op1,1(a0)	;\
	HAZARD_CACHE

/* specials for cache initialisation            */
/* All cache initialization is done by index ops*/
/* Two-way set associativity is considered here */
#define doop1lw(op1) \
	lw	zero,0(a0)
#define doop1lw1(op1) \
	cache	op1,0(a0)  ; \
	HAZARD_CACHE	   ; \
	cache   op1,1(a0)  ; \
	lw	zero,0(a0) ; \
	cache	op1,0(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op1,1(a0)  ; \
	HAZARD_CACHE
#define doop121(op1,op2) \
	cache	op1,0(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op1,1(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op2,0(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op2,1(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op1,0(a0)  ; \
	HAZARD_CACHE	   ; \
	cache	op1,1(a0)  ; \
	HAZARD_CACHE

#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
	.set	noreorder ;		\
10: 	doop##tag##ops ;	\
	bne     minaddr,maxaddr,10b ;	\
	add   	minaddr,linesize ;	\
	.set	reorder

/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
 	blez	n,11f ;			\
	addu	n,kva ;			\
	_align(kva, n, cacheLineSize) ; \
	_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:

#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
	_mincache(n, cacheSize);	\
 	blez	n,11f ;			\
	addu	n,kva ;			\
	_align(kva, n, cacheLineSize) ; \
	_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:

/* Cache macro for two-way set associative cache index operations */
#define i10cacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
	srl	cacheSize,1	; \
	_mincache(n, cacheSize)	; \
	blez	n,11f		; \
	addu	n,kva		; \
	_align(kva, n, cacheLineSize); \
	_oploopn(kva, n, cacheLineSize, tag, ops); \
11:
	
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
	vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))

#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
	icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))

#define i10cacheop(kva, n, cacheSize, cacheLineSize, op) \
	i10cacheopn(kva, n, cacheSize, cacheLineSize, 10, (op))

	.text

	.globl  GTEXT(cacheR10kReset)		/* low level cache init    */
	.globl	GTEXT(cacheR10kRomTextUpdate)	/* cache-text-update */
	.globl	GTEXT(cacheR10kDCFlushInvalidateAll) /* flush entire d-cache    */
	.globl	GTEXT(cacheR10kDCFlushInvalidate) /* flush d-cache locations */
	.globl	GTEXT(cacheR10kICInvalidateAll)	/* inval i-cache locations */
	.globl	GTEXT(cacheR10kICInvalidate)	/* inval i-cache locations */
	.globl	GTEXT(cacheR10kSync)		/* cache sync */
	.globl	GTEXT(cacheR10kVirtPageFlush)	/* flush cache on MMU page unmap */
	.globl	GTEXT(cacheR10kDCLock)		/* data cache lock */
	.globl	GTEXT(cacheR10kICLock)		/* inst. cache lock */

	.globl	GDATA(cacheR10kDCacheSize)	/* d-cache size		*/
	.globl	GDATA(cacheR10kICacheSize)	/* i-cache size		*/
	.globl	GDATA(cacheR10kSCacheSize)	/* secondary cache size	*/

	.globl	GDATA(cacheR10kDCacheLineSize)	/* d-cache line size	*/
	.globl	GDATA(cacheR10kICacheLineSize)	/* i-cache line size	*/
	.globl	GDATA(cacheR10kSCacheLineSize)	/* s-cache line size	*/

	.data
	.align	4
cacheR10kICacheSize:
	.word	0
cacheR10kDCacheSize:
	.word	0
cacheR10kSCacheSize:
	.word	0
cacheR10kICacheLineSize:
	.word	0
cacheR10kDCacheLineSize:
	.word	0
cacheR10kSCacheLineSize:
	.word	0
	
	.text
	.set	reorder

/******************************************************************************
*
* cacheR10kReset - low level initialisation of the R10000 primary caches
*
* This routine initialises the R10000 primary caches to ensure that they
* have good parity.  It must be called by the ROM before any cached locations
* are used to prevent the possibility of data with bad parity being written to
* memory.
*
* RETURNS: N/A
*

* void cacheR10kReset (initMem)

*/
	.ent	cacheR10kReset
FUNC_LABEL(cacheR10kReset)
	mfc0	v0,C0_SR
	HAZARD_CP_READ
	
	and	v1,v0,SR_BEV
	or	v1,SR_DE
	mtc0	v1,C0_SR
	
	/* set invalid tag */
	mtc0	zero,C0_TAGLO
	mtc0	zero,C0_TAGHI
	HAZARD_CACHE_TAG
		
	/*
	 * The caches are probably in an indeterminate state, so we force
	 * good parity into them by doing an invalidate, load/fill, 
	 * invalidate for each line.  We do an invalidate of each line in
	 * the cache before we perform any fills, because we need to 
	 * ensure that each way of an n-way associative cache is invalid
	 * before performing the first Fill_I cacheop.
	 */

	/* 1: initialize icache tags */
	li	a0,K0BASE
	move	a2,t0		# icacheSize
	move	a3,t1		# icacheLineSize
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Store_Tag_I)

	/* 2: fill icache */
	li	a0,K0BASE
	move	a2,t0		# icacheSize
	move	a3,t1		# icacheLineSize
	move	a1,a2
	icacheop(a0,a1,a2,a3,Fill_I)

	/* 3: clear icache tags */
	li	a0,K0BASE
	move	a2,t0		# icacheSize
	move	a3,t1		# icacheLineSize
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Store_Tag_I)

	/* 1: initialize dcache tags */
	li	a0,K0BASE
	move	a2,t2		# dcacheSize
	move	a3,t3		# dcacheLineSize
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Store_Tag_D)

	/* 1: fill dcache */
	li	a0,K0BASE
	move	a2,t2		# dcacheSize
	move	a3,t3		# dcacheLineSize
	move	a1,a2
	icacheopn(a0,a1,a2,a3,1lw,(dummy))

	/* 1: clear dcache tags */
	li	a0,K0BASE
	move	a2,t2		# dcacheSize
	move	a3,t3		# dcacheLineSize
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Store_Tag_D)
	
	/* initialize secondary cache if present */
	blez	t4,1f
	
	li	a0,K0BASE
	move	a2,t4
	move	a3,t5
	move	a1,a2
	icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_SD, Create_Dirty_Exc_SD))
1:
	mtc0	v0,C0_SR
	HAZARD_CP_WRITE
	j	ra
	.end	cacheR10kReset


/******************************************************************************
*
* cacheR10kRomTextUpdate - cache text update like functionality from the bootApp
*
*	a0	i-cache size
*	a1	i-cache line size
*	a2	d-cache size
*	a3	d-cache line size
*
* RETURNS: N/A
*

* void cacheR10kRomTextUpdate ()

*/
	.ent	cacheR10kRomTextUpdate
FUNC_LABEL(cacheR10kRomTextUpdate)
	/* Save I-cache parameters */
	move	t0,a0
	move	t1,a1

	/* Check for primary data cache */
	blez	a2,99f

	/* Flush-invalidate primary data cache */
	li	a0,K0BASE
	move	a1,a2
	i10cacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
99:
	/* replace I-cache parameters */
	move	a2,t0
	move	a3,t1
	
	/* Check for primary instruction cache */
	blez	a0,99f
	
	/* Invalidate primary instruction cache */
	li	a0,K0BASE