dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

LOCAL char w_fs_ft[] = "w,fs,ft";
LOCAL char fd_n[] = "fd,n";
LOCAL char fd_fr_fs_ft[] = "fd,fr,fs,ft";
LOCAL char rd_rs_d[] = "rd,rs,d";
LOCAL char fd_fs_d[] = "fd,fs,d";
LOCAL char fd_fs_rt[] = "fd,fs,rt";
LOCAL char H_n[] = "H,n";
LOCAL char H_m[] = "H,m";
LOCAL char fs_n[] = "fs,n"; 
LOCAL char fd_fs[] = "fd,fs";
LOCAL char fd_fs_ft[] = "fd,fs,ft";
LOCAL char fs_ft[] = "fs,ft";
LOCAL char ft_m[] = "ft,m";
LOCAL char g[] = "g";		
LOCAL char j[] = "j";		/* Absolute Jump */
LOCAL char null[] = "";
LOCAL char rd[] = "rd";
LOCAL char rd_rs[] = "rd,rs";
LOCAL char rd_rs_rt[] = "rd,rs,rt";
LOCAL char rd_rt[] = "rd,rt";
LOCAL char rd_rt_rs[] = "rd,rt,rs";
LOCAL char rd_rt_s[] = "rd,rt,s";
LOCAL char rs[] = "rs";
LOCAL char rs_b[] = "rs,b";
LOCAL char rs_i[] = "rs,i";
LOCAL char rs_rt[] = "rs,rt";
LOCAL char rs_rt_b[] = "rs,rt,b";
LOCAL char rt_P[] = "rt,P";
LOCAL char rt_0[] = "rt,0";
LOCAL char rt_0_sel[] = "rt,0,i0";
LOCAL char rt_1[] = "rt,1";
LOCAL char rt_fs[] = "rt,fs";
LOCAL char rt_fs_sel[] = "rt,fs,i0";
LOCAL char rt_i[] = "rt,i";
LOCAL char rt_m[] = "rt,m";
LOCAL char rt_rs_i[] = "rt,rs,i";
LOCAL char rt_rs_u[] = "rt,rs,u";
LOCAL char rt_u[] = "rt,u";
/* VR5400 Multi-media insn formats */
LOCAL char vd_vs_vt[] = "vd,vs,vt";
LOCAL char vd_vs_vt_sel[] = "vd,vs,vt[ve]";
LOCAL char vd_vs_vt_imm[] = "vd,vs,C";
LOCAL char vd_vs_vt_vi[] = "vd,vs,vt,vi";
LOCAL char vd_C[] = "vd,C";
LOCAL char vs_vt[] = "vs,vt";
LOCAL char vs_vt_sel[] = "vs,vt[ve]";
LOCAL char vs_vt_imm[] = "vs,C";
LOCAL char vd[] = "vd";
LOCAL char vs[] = "vs";
LOCAL char vi[] = "vi";

LOCAL INST itab[] =
    {

    /* R5400 new insns; most have three formats depending on SEL field  */
    {"pickf.ob",	MMTYPE_VEC(2),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"pickt.ob",	MMTYPE_VEC(3),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"min.ob",		MMTYPE_VEC(6),	MMVECMSK, vd_vs_vt, CPU_VR5400}, 
    {"max.ob",		MMTYPE_VEC(7),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"sub.ob",		MMTYPE_VEC(10),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"add.ob",		MMTYPE_VEC(11),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"and.ob",		MMTYPE_VEC(12),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"xor.ob",		MMTYPE_VEC(13),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"or.ob",		MMTYPE_VEC(14),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"nor.ob",		MMTYPE_VEC(15),	MMVECMSK, vd_vs_vt, CPU_VR5400},
    {"mul.ob",		MMTYPE_VEC(48),	MMVECMSK, vd_vs_vt, CPU_VR5400},

    {"pickf.ob",	MMTYPE(2),	MMSELMSK, vd_vs_vt, CPU_VR5400},
    {"pickt.ob",	MMTYPE(3),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"min.ob",		MMTYPE(6),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400}, 
    {"max.ob",		MMTYPE(7),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"sub.ob",		MMTYPE(10),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"add.ob",		MMTYPE(11),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"and.ob",		MMTYPE(12),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"xor.ob",		MMTYPE(13),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"or.ob",		MMTYPE(14),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"nor.ob",		MMTYPE(15),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"sll.ob",		MMTYPE(16),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"srl.ob",		MMTYPE(18),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},
    {"mul.ob",		MMTYPE(48),	MMSELMSK, vd_vs_vt_sel, CPU_VR5400},

    {"pickf.ob",	MMTYPE_IMM(2),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"pickt.ob",	MMTYPE_IMM(3),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"min.ob",		MMTYPE_IMM(6),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400}, 
    {"max.ob",		MMTYPE_IMM(7),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"sub.ob",		MMTYPE_IMM(10),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"add.ob",		MMTYPE_IMM(11),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"and.ob",		MMTYPE_IMM(12),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"xor.ob",		MMTYPE_IMM(13),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"or.ob",		MMTYPE_IMM(14),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"nor.ob",		MMTYPE_IMM(15),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"sll.ob",		MMTYPE_IMM(16),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"srl.ob",		MMTYPE_IMM(18),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},
    {"mul.ob",		MMTYPE_IMM(48),	MMIMMMSK, vd_vs_vt_imm, CPU_VR5400},

    {"c.lt.ob",		MMTYPE_VEC(4),	MMVECMSK|MMCMSK, vs_vt, CPU_VR5400},
    {"c.le.ob",		MMTYPE_VEC(5),	MMVECMSK|MMCMSK, vs_vt, CPU_VR5400},
    {"c.eq.ob",		MMTYPE_VEC(1),	MMVECMSK|MMCMSK, vs_vt, CPU_VR5400},

    {"c.lt.ob",		MMTYPE(4),     MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},
    {"c.le.ob",		MMTYPE(5),     MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},
    {"c.eq.ob",		MMTYPE(1),     MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},

    {"c.lt.ob",		MMTYPE_IMM(4), MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},
    {"c.le.ob",		MMTYPE_IMM(5), MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},
    {"c.eq.ob",		MMTYPE_IMM(1), MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},

    {"muls.ob",		MMTYPE_MUL_VEC(0,50),	MMVECMSK|MMCMSK, vs_vt, 
     CPU_VR5400},
    {"mulsl.ob",	MMTYPE_MUL_VEC(16,50),	MMVECMSK|MMCMSK, vs_vt, 
     CPU_VR5400},
    {"mula.ob",		MMTYPE_MUL_VEC(0,51),	MMVECMSK|MMCMSK, vs_vt, 
     CPU_VR5400},
    {"mull.ob",		MMTYPE_MUL_VEC(16,51),	MMVECMSK|MMCMSK, vs_vt, 
     CPU_VR5400},

    {"muls.ob",		MMTYPE_MUL(0,50),	MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},
    {"mulsl.ob",	MMTYPE_MUL(16,50),	MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},
    {"mula.ob",		MMTYPE_MUL(0,51),	MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},
    {"mull.ob",		MMTYPE_MUL(16,51),	MMSELMSK|MMCMSK, vs_vt_sel, CPU_VR5400},

    {"muls.ob",		MMTYPE_MUL_IMM(0,50),	MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},
    {"mulsl.ob",	MMTYPE_MUL_IMM(16,50),	MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},
    {"mula.ob",		MMTYPE_MUL_IMM(0,51),	MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},
    {"mull.ob",		MMTYPE_MUL_IMM(16,51),	MMIMMMSK|MMCMSK, vs_vt_imm, CPU_VR5400},

    /* remaining multimedia insn's have only one form */
    {"racl.ob",		MMTYPE_AC(0,63),	MM4MSK, vd, CPU_VR5400},
    {"racm.ob",		MMTYPE_AC(4,63),	MM4MSK, vd, CPU_VR5400},
    {"rach.ob",		MMTYPE_AC(8,63),	MM4MSK, vd, CPU_VR5400},

#if 0 /* XXX VR5400 doc - wrong! */
    {"shfl.pach.ob",	MMTYPE_AC(4,31),	MM1MSK, vd_vs_vt, CPU_VR5400},
    {"shfl.pacl.ob",	MMTYPE_AC(5,31),	MM1MSK, vd_vs_vt, CPU_VR5400},
    {"shfl.mixh.ob",	MMTYPE_AC(6,31),	MM1MSK, vd_vs_vt, CPU_VR5400},
    {"shfl.mixl.ob",	MMTYPE_AC(7,31),	MM1MSK, vd_vs_vt, CPU_VR5400},
#else /* cygnus gnu opcode; unique */
    {"shfl.pach.ob",	0x4900001f, 0xffe0003f, vd_vs_vt, CPU_VR5400},
    {"shfl.pacl.ob",	0x4940001f, 0xffe0003f, vd_vs_vt, CPU_VR5400},
    {"shfl.mixh.ob",	0x4980001f, 0xffe0003f, vd_vs_vt, CPU_VR5400},
    {"shfl.mixl.ob",	0x49c0001f, 0xffe0003f, vd_vs_vt, CPU_VR5400},
#endif

    {"rzu.ob",		MMTYPE(32),	MM5MSK, vd_C, CPU_VR5400},

    {"wach.ob",		MMTYPE_AC(8,62),	MM6MSK, vs, CPU_VR5400},
    {"wacl.ob",		MMTYPE_AC(0,62),	MM3MSK, vs_vt, CPU_VR5400},

    {"alni.ob",		MMTYPE(24),	MMALNIMSK, vd_vs_vt_vi, CPU_VR5400},

    {"dbreak",          JTYPE(0x1c,0x3f), IMASK(0,0,0x3f), null,  CPU_VR5400},
    {"dret",            JTYPE(0x1c,0x3e), IMASK(0,0,0x3f), null,  CPU_VR5400},

    /* XXX unique forms...*/
    {"mfpc",            0x4000c801,	0xffe0ffc1, rt_P,  CPU_VR5400},
    {"mfps",            0x4000c800,	0xffe0ffc1, rt_P,  CPU_VR5400},
    {"mtpc",            0x4080c801,	0xffe0ffc1, rt_P,  CPU_VR5400},
    {"mtps",            0x4080c800,	0xffe0ffc1, rt_P,  CPU_VR5400},
    {"mfdr",            0x7000003d,	0xffe007ff, rt_0,  CPU_VR5400},
    {"mtdr",            0x7080003d,	0xffe007ff, rt_0,  CPU_VR5400},

    
    {"macc",		MMTYPE_MACM(344),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"macchi",		MMTYPE_MACM(856),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"macchiu",		MMTYPE_MACM(857),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"maccu",		MMTYPE_MACM(345),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"msac",		MMTYPE_MACM(472),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"msachi",		MMTYPE_MACM(984),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"msachiu",		MMTYPE_MACM(985),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"msacu",		MMTYPE_MACM(473),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mul",		MMTYPE_MACM(88), 	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulhi",		MMTYPE_MACM(600),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulhiu",		MMTYPE_MACM(601),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulu",		MMTYPE_MACM(89), 	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"muls",		MMTYPE_MACM(216),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulshi",		MMTYPE_MACM(728),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulshiu",		MMTYPE_MACM(729),	MACMMSK, rd_rs_rt, CPU_VR5400},
    {"mulsu",		MMTYPE_MACM(217),	MACMMSK, rd_rs_rt, CPU_VR5400},

    /* XXX 5400 documents dror & dror32 w/ identical bits; gnu uses: */
    {"dror32",		MMTYPE_ROR(62),		MM1MSK, rd_rt_s, CPU_VR5400},
    {"dror",		MMTYPE_ROR(54),		MM1MSK, rd_rt_s, CPU_VR5400},
    {"dror",		MMTYPE_ROR(62),		MM1MSK, rd_rt_s, CPU_VR5400},
    {"ror",		MMTYPE_ROR(2),	 	MM1MSK, rd_rt_s, CPU_VR5400},

#if 0 /* this is the vr5400 doc version */
    {"drorv",		MMTYPE_ROR(22),		RORVMSK, rd_rt_rs, CPU_VR5400},
    {"rorv",		MMTYPE_ROR(6),	 	RORVMSK, rd_rt_rs, CPU_VR5400},
#else /* the cygnus gnu opcode encoding: JTYPE(0,0x56) */
    {"drorv",		0x00000056, 0xfc0007ff, rd_rt_rs, CPU_VR5400},
    {"rorv",		0x00000046, 0xfc0007ff, rd_rt_rs, CPU_VR5400},
#endif
    /* End R5400 new insns */


    /* Coprocessor 0 operations */
    {"tlbr",	ITYPE(16,0x10,0,0x01), (unsigned long) (~0), null},
    {"tlbwi",	ITYPE(16,0x10,0,0x02), (unsigned long) (~0), null},
    {"tlbwr",	ITYPE(16,0x10,0,0x06), (unsigned long) (~0), null},
    {"tlbp",	ITYPE(16,0x10,0,0x08), (unsigned long) (~0), null},
    {"rfe",	ITYPE(16,0x10,0,0x10), (unsigned long) (~0), null},
    {"eret",	ITYPE(16,0x10,0,0x18), (unsigned long) (~0), null},
    {"dret",	ITYPE(16,0x10,0,0x1f), (unsigned long) (~0), null},
    {"waiti",	ITYPE(16,0x10,0,0x20), (unsigned long) (~0), null, CPU_CW4011},

    /* Coprocessor 1 operations */
    {"add.s",	COP1T(0,0),	COP1TMSK, fd_fs_ft},
    {"add.d",	COP1T(1,0),	COP1TMSK, fd_fs_ft},
    {"add.e",	COP1T(2,0),	COP1TMSK, fd_fs_ft},
    {"add.q",	COP1T(3,0),	COP1TMSK, fd_fs_ft},
    {"add.w",	COP1T(4,0),	COP1TMSK, fd_fs_ft},
    {"add.l",	COP1T(5,0),	COP1TMSK, fd_fs_ft},

    {"sub.s",	COP1T(0,1),	COP1TMSK, fd_fs_ft},
    {"sub.d",	COP1T(1,1),	COP1TMSK, fd_fs_ft},
    {"sub.e",	COP1T(2,1),	COP1TMSK, fd_fs_ft},
    {"sub.q",	COP1T(3,1),	COP1TMSK, fd_fs_ft},
    {"sub.w",	COP1T(4,1),	COP1TMSK, fd_fs_ft},
    {"sub.l",	COP1T(5,1),	COP1TMSK, fd_fs_ft},

    {"mul.s",	COP1T(0,2),	COP1TMSK, fd_fs_ft},
    {"mul.d",	COP1T(1,2),	COP1TMSK, fd_fs_ft},
    {"mul.e",	COP1T(2,2),	COP1TMSK, fd_fs_ft},
    {"mul.q",	COP1T(3,2),	COP1TMSK, fd_fs_ft},
    {"mul.w",	COP1T(4,2),	COP1TMSK, fd_fs_ft},
    {"mul.l",	COP1T(5,2),	COP1TMSK, fd_fs_ft},

    {"div.s",	COP1T(0,3),	COP1TMSK, fd_fs_ft},
    {"div.d",	COP1T(1,3),	COP1TMSK, fd_fs_ft},
    {"div.e",	COP1T(2,3),	COP1TMSK, fd_fs_ft},
    {"div.q",	COP1T(3,3),	COP1TMSK, fd_fs_ft},
    {"div.w",	COP1T(4,3),	COP1TMSK, fd_fs_ft},
    {"div.l",	COP1T(5,3),	COP1TMSK, fd_fs_ft},

    {"sqrt.s",	COP1T(0,4),	COP1BMSK, fd_fs},
    {"sqrt.d",	COP1T(1,4),	COP1BMSK, fd_fs},
    {"sqrt.e",	COP1T(2,4),	COP1BMSK, fd_fs},
    {"sqrt.q",	COP1T(3,4),	COP1BMSK, fd_fs},
    {"sqrt.w",	COP1T(4,4),	COP1BMSK, fd_fs},
    {"sqrt.l",	COP1T(5,4),	COP1BMSK, fd_fs},

    {"abs.s",	COP1B(0,5),	COP1BMSK, fd_fs},
    {"abs.d",	COP1B(1,5),	COP1BMSK, fd_fs},
    {"abs.e",	COP1B(2,5),	COP1BMSK, fd_fs},
    {"abs.q",	COP1B(3,5),	COP1BMSK, fd_fs},
    {"abs.w",	COP1B(4,5),	COP1BMSK, fd_fs},
    {"abs.l",	COP1B(5,5),	COP1BMSK, fd_fs},

    {"mov.s",	COP1B(0,6),	COP1BMSK, fd_fs},
    {"mov.d",	COP1B(1,6),	COP1BMSK, fd_fs},
    {"mov.e",	COP1B(2,6),	COP1BMSK, fd_fs},
    {"mov.q",	COP1B(3,6),	COP1BMSK, fd_fs},

    {"neg.s",	COP1B(0,7),	COP1BMSK, fd_fs},
    {"neg.d",	COP1B(1,7),	COP1BMSK, fd_fs},
    {"neg.e",	COP1B(2,7),	COP1BMSK, fd_fs},
    {"neg.q",	COP1B(3,7),	COP1BMSK, fd_fs},
    {"neg.w",	COP1B(4,7),	COP1BMSK, fd_fs},
    {"neg.l",	COP1B(5,7),	COP1BMSK, fd_fs},

    {"round.l.s",	COP1B(0,8),	COP1BMSK, fd_fs},
    {"round.l.d",	COP1B(1,8),	COP1BMSK, fd_fs},
    {"round.l.e",	COP1B(2,8),	COP1BMSK, fd_fs},
    {"round.l.q",	COP1B(3,8),	COP1BMSK, fd_fs},

    {"trunc.l.s",	COP1B(0,9),	COP1BMSK, fd_fs},
    {"trunc.l.d",	COP1B(1,9),	COP1BMSK, fd_fs},
    {"trunc.l.e",	COP1B(2,9),	COP1BMSK, fd_fs},
    {"trunc.l.q",	COP1B(3,9),	COP1BMSK, fd_fs},

    {"ceil.l.s",	COP1B(0,10),	COP1BMSK, fd_fs},
    {"ceil.l.d",	COP1B(1,10),	COP1BMSK, fd_fs},
    {"ceil.l.e",	COP1B(2,10),	COP1BMSK, fd_fs},
    {"ceil.l.q",	COP1B(3,10),	COP1BMSK, fd_fs},

    {"floor.l.s",	COP1B(0,11),	COP1BMSK, fd_fs},
    {"floor.l.d",	COP1B(1,11),	COP1BMSK, fd_fs},
    {"floor.l.e",	COP1B(2,11),	COP1BMSK, fd_fs},
    {"floor.l.q",	COP1B(3,11),	COP1BMSK, fd_fs},

    {"round.w.s",	COP1B(0,12),	COP1BMSK, fd_fs},
    {"round.w.d",	COP1B(1,12),	COP1BMSK, fd_fs},
    {"round.w.e",	COP1B(2,12),	COP1BMSK, fd_fs},
    {"round.w.q",	COP1B(3,12),	COP1BMSK, fd_fs},

    {"trunc.w.s",	COP1B(0,13),	COP1BMSK, fd_fs},
    {"trunc.w.d",	COP1B(1,13),	COP1BMSK, fd_fs},
    {"trunc.w.e",	COP1B(2,13),	COP1BMSK, fd_fs},
    {"trunc.w.q",	COP1B(3,13),	COP1BMSK, fd_fs},

    {"ceil.w.s",	COP1B(0,14),	COP1BMSK, fd_fs},
    {"ceil.w.d",	COP1B(1,14),	COP1BMSK, fd_fs},
    {"ceil.w.e",	COP1B(2,14),	COP1BMSK, fd_fs},
    {"ceil.w.q",	COP1B(3,14),	COP1BMSK, fd_fs},

    {"floor.w.s",	COP1B(0,15),	COP1BMSK, fd_fs},
    {"floor.w.d",	COP1B(1,15),	COP1BMSK, fd_fs},
    {"floor.w.e",	COP1B(2,15),	COP1BMSK, fd_fs},
    {"floor.w.q",	COP1B(3,15),	COP1BMSK, fd_fs},

    {"movf.s", COP1B_MIPS4(0,0,17), COP1BMSK_MIPS4, fd_fs_d, CPU_MIPS4},
    {"movf.d", COP1B_MIPS4(1,0,17), COP1BMSK_MIPS4, fd_fs_d, CPU_MIPS4},

    {"movt.s", COP1B_MIPS4(0,1,17), COP1BMSK_MIPS4, fd_fs_d, CPU_MIPS4},
    {"movt.d", COP1B_MIPS4(1,1,17), COP1BMSK_MIPS4, fd_fs_d, CPU_MIPS4},

    {"movz.s", COP1B(0,18), COP1BMSK_MIPS4, fd_fs_rt, CPU_MIPS4},
    {"movz.d", COP1B(1,18), COP1BMSK_MIPS4, fd_fs_rt, CPU_MIPS4},