dsmlib.c

VxWorks BSP框架源代码包含头文件和驱动

/* dsmips.c - MIPS disassembler */

/* Copyright 1984-2001 Wind River Systems, Inc. */

#include "copyright_wrs.h"

/*
 * This file has been developed or significantly modified by the
 * MIPS Center of Excellence Dedicated Engineering Staff.
 * This notice is as per the MIPS Center of Excellence Master Partner
 * Agreement, do not remove this notice without checking first with
 * WR/Platforms MIPS Center of Excellence engineering management.
 */

/*
modification history
--------------------
01c,06dec01,agf  add 3 operand support for mtc./mfc.
01b,16jul01,ros  add CofE comment
01a,11jul01,mem  written based on 01n of host/src/tgtsvr/disassembler/dsmMips.c
*/

/*
DESCRIPTION
This library contains everything necessary to print MIPS IV object 
code in assembly language format. 

The programming interface is via dsmMipsInstGet, which prints a single
disassembled instruction, and dsmMipsInstSizeGet, which will tell you
how big an instruction is.

To disassemble from the shell, use l(2), which calls this
library to do the actual work.  See dbgLib(1) for details.

ADDRESS PRINTING ROUTINE
Many assembly language operands are addresses.  In order to print these
addresses symbolically, dsmMipsInstGet calls a user-supplied routine, passed as
a parameter, to do the actual printing.  The routine should be declared as:

.CS
    void prtAddress (int address)
.CE

When called, the routine prints the address on standard out in either
numeric or symbolic form.  For example, the address-printing routine used
by l(2) looks up the address in the system symbol table and prints the
symbol associated with it, if there is one.  If not, it prints the address
as a hex number.

If the <prtAddress> argument to dsmMipsInstGet is NULL, a default print routine
is used, which prints the address as a hexadecimal number.

The directive DC.W (declare word) is printed for unrecognized instructions.

DEFICIENCIES

The address operand printing routine interface has been retained although
it will support only jumps and branches ("lui" and "addiu" pairs are
not coupled here so these cannot be resolved symbolically).  This interface
is provided so that a caller could look up the address operand in the symbol
table and print its symbol name rather than raw address.
*/

/* includes */

#ifdef HOST
#include <string.h>
#include <stdlib.h>

#include "host.h"
#include "dsmMips.h"
#include "cputypes.h"
#include "stdio.h"
#include "symbol.h"
#else
#include "vxWorks.h"
#include "dsmLib.h"
#include "errnoLib.h"
#include "symbol.h"
#include "stdio.h"
#include "sysSymTbl.h"
#include "arch/mips/dbgMipsLib.h"
#endif

/* defines */

#define MAX_LINE_LEN	1000	/* max line length for an instruction        */
#define BUF_MAX_SIZE    30      /* max size of buffer to write in            */

/* 

The CPU bits defined below can be used to identify instructions which
are only valid on a particular set of CPU types.  At some point in the
future it might be valuable to add bits which identify CPU groups such
as ISA, ISA2, etc.  If you add any entry to this list, a corresponding
entry needs to be made to the CPUMASK, defined below.

*/

#define CPU_ANY		(0)
#define CPU_MIPS1	(1 << 0)
#define CPU_MIPS2	(1 << 1)
#define CPU_MIPS3	(1 << 2)
#define CPU_MIPS4	(1 << 3)
#define CPU_MIPS32	(1 << 4)
#define CPU_MIPS64	(1 << 5)

#define CPU_CW4011	(0)		/* dummy */
#define CPU_R4650	(0)		/* dummy */
#define CPU_VR5400	(0)		/* dummy */

#ifndef HOST
#if (CPU==MIPS32)
#define	CPUMASK		(CPU_MIPS1 | CPU_MIPS2 | CPU_MIPS32)
#elif (CPU==MIPS64)
#define CPUMASK		\
    (CPU_MIPS1 | CPU_MIPS2 | CPU_MIPS3 | CPU_MIPS4 | CPU_MIPS32 | CPU_MIPS64)
#else
#error "Illegal CPU value"
#endif
#endif

/*

The following tables represent intruction opcodes and subtypes.
Each table entry consists of four elements:
	-an opcode mnemonic string to be printed if a match occurs,
	-the bit pattern which the relevent part of the opcode is
	 matched with,
	-a mask field to be applied to the instruction to extract,
	-a format string describing the instruction operands.

The inst table is searched linearly to find the first matching instruction.
A match is made when the extracted part of an instruction matches
the 2nd field.  Overloaded instructions such as sll/nop are resolved by
inserting the special case instruction before the general case.

*/

#define ITYPE(op,rs,rt,immed) ((unsigned long) ( ( (op)<<26) | ( ( rs)<<21) | \
						 ( (rt)<<16) | immed))
#define RTYPE(rs,rt,rd,v) ITYPE(0,rs,rt,rd<<11|v)
#define JTYPE(op,val) ( (unsigned long) ( ( (op)<<26) | val))
#define MTYPE(op,rs,rt,rd,v) ITYPE(op,rs,rt,rd<<11|v)

#define RMASK(rs,rt,rd,v) ITYPE(0x3f,rs,rt,rd<<11|v)
#define IMASK(a,b,c)	  ITYPE(0x3f,a,b,c)
#define MMASK(a,b,c)	  ITYPE(0x3f,a,b,((c)<<11)|v)

#define COP1T(fmt,code) ( (unsigned long) ( (17 << 26) | (1 << 25) | \
					   (fmt << 21) | code))
#define COP1B(fmt,code) COP1T(fmt,code)
#define COP1TMSK	( (unsigned long) ( (0x3f << 26) | (1 << 25) | \
					   (0xf << 21) | 0x3f))
#define COP1BMSK	( (unsigned long) (COP1TMSK | (0x1f << 16)))
#define COP1CMPMSK	( (unsigned long) (COP1TMSK | (0x1f << 6)))

#define JTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define JTYPE_TARGET(code)      (code & 0x03ffffff)
#define ITYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define ITYPE_RS(code)  ((code & 0x03e00000) >> 21)
#define ITYPE_RT(code)  ((code & 0x001f0000) >> 16)
#define ITYPE_I(code)   ((unsigned long) (short)(code & 0x0000ffff))
#define UTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define UTYPE_RS(code)  ((code & 0x03e00000) >> 21)
#define UTYPE_RT(code)  ((code & 0x001f0000) >> 16)
#define UTYPE_U(code)   (code & 0x0000ffff)
#define RTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define RTYPE_RS(code)  ((code & 0x03e00000) >> 21)
#define RTYPE_RT(code)  ((code & 0x001f0000) >> 16)
#define RTYPE_RD(code)  ((code & 0x0000f800) >> 11)
#define RTYPE_S(code)   ((code & 0x000007c0) >> 6)
#define RTYPE_FUNC(code)        (code & 0x0000003f)
#define FTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define FTYPE_FMT(code) ((code & 0x01d00000) >> 21)
#define FTYPE_FR(code)	((code & 0x03e00000) >> 21)
#define FTYPE_FT(code)  ((code & 0x001f0000) >> 16)
#define FTYPE_FS(code)  ((code & 0x0000f800) >> 11)
#define FTYPE_FD(code)  ((code & 0x000007c0) >> 6)
#define FTYPE_FUNC(code)        (code & 0x0000003f)
#define CTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define CTYPE_CO(code)  ((code & 0x02000000) >> 25)
#define CTYPE_COFUNC(code)      (code & 0x01ffffff)
#define TTYPE_OP(code)  ((code & 0xfc000000) >> 26)
#define TTYPE_CODE(code)        ((code & 0x03ffffc0) >> 6)
#define TTYPE_FUNC(code)        (code & 0x0000003f)

#define COP1B_MIPS4(fmt,tf,code)    ((17 << 26) | (1 << 25) | (fmt << 21) | (tf <<16)|code)
#define COP1BMSK_MIPS4   (COP1TMSK | (0x03 << 6))
#define COP1CMPMSK_MIPS4 (COP1TMSK | (0x03 << 6))

#define COP1B_MIPS4(fmt,tf,code)    ((17 << 26) | (1 << 25) | (fmt << 21) | (tf <<16)|code)
#define COP1BMSK_MIPS4   (COP1TMSK | (0x03 << 6))
#define COP1CMPMSK_MIPS4 (COP1TMSK | (0x03 << 6))

#define MIPS4_RCC(code)	((code & 0x001c0000) >> 18)
#define MIPS4_WCC(code)	((code & 0x00000700) >> 8)

#define MMTYPE(code)		((unsigned long) ((18 << 26) | (code)))
#define MMTYPE_VEC(code)	((unsigned long) ((18 << 26) | \
				 (0xb << 22) | (code)))
#define MMTYPE_IMM(code)	((unsigned long) ((18 << 26) | \
				 (0xf << 22) | (code)))
#define MMTYPE_AC(acc,code)	((unsigned long) ((18 << 26) | \
				 ((acc) << 22) | (code)))

#define MMTYPE_MUL(acc,code)	((unsigned long) ((18 << 26) | \
				 ((acc) << 6) | (code)))
#define MMTYPE_MUL_VEC(acc,code) \
    ((unsigned long) ((18 << 26) | (0xb << 22) | ((acc) << 6) | (code)))
#define MMTYPE_MUL_IMM(acc,code) \
    ((unsigned long) ((18 << 26) | (0xf << 22) | ((acc) << 6) | (code)))

#define MMTYPE_MACM(code)	((unsigned long) (code))
#define MMTYPE_ROR(code)	((unsigned long) (1 << 21) | (code))

#define MMVECMSK		(0xffe0003f)	/* vector-vector */
#define MMIMMMSK		(0xffe0003f)	/* vector-immediate */
#define MMSELMSK		(0xfe20003f)	/* vector-scalar */
#define MMCMSK			(0x1f << 6)	/* used by c.XX.ob */

#define MM1MSK		((unsigned long) ((0x3f << 26) | (0x01 << 21) |(0x3f)))
#define MM2MSK		(MM1MSK | (0x1f << 6))
#define MM3MSK		(MM2MSK | (0xf << 21))
#define MM4MSK		(MM1MSK | (0x7fff << 11))
#define MM5MSK		(MM1MSK | (0x1f << 11))
#define MM6MSK		(MM2MSK | (0x3ff << 16))
#define MMALNIMSK	((unsigned long) ((0xff << 24) | (0x3f)))

#define RORVMSK		((unsigned long) ((0x3f << 26) | (0x1f << 6) | (0x3f)))
#define MACMMSK		((unsigned long) ((0x3f << 26) |(0x7ff)))

#define VTYPE_OP(code)		(((code) & 0xfc000000) >> 26)
#define VTYPE_SEL(code)		(((code) & 0x03c00000) >> 22)
#define VTYPE_ACC(code)		(((code) & 0x03c00000) >> 22)
#define VTYPE_IMM(code)		(((code) & 0x01f00000) >> 21)
#define VTYPE_VT(code)		(((code) & 0x001f0000) >> 16)
#define VTYPE_VS(code)		(((code) & 0x0000f800) >> 11)
#define VTYPE_VD(code)		(((code) & 0x000007c0) >> 6)
#define VTYPE_FUNC(code)	((code) & 0x0000003f)

/* mips16 defines and strings describing operand formats  */

#define I16_OPCODE_MASK     0xf800
#define I16_RTYPE_RX(code)  ((code & 0x0700) >> 8)
#define I16_RTYPE_RY(code)  ((code & 0x00e0) >> 5)
#define I16_RTYPE_RZ(code)  ((code & 0x001c) >> 2)
#define I16_ITYPE_I4(code)  (code & 0xf)
#define I16_ITYPE_I5(code)  (code & 0x1f)
#define I16_ITYPE_I8(code)  (code & 0xff)
#define I16_ITYPE_I11(code) (code & 0x7ff)

#define ITYPE16_1(op,rx,ry,rz,immed) \
	( ((op) << 11) | ((rx) << 8) | ((ry) << 5) | ((rz) << 2) | immed)

#define RMASK16(rx,ry,rz,immed) ITYPE16_1(0x1f,rx,ry,rz,immed)

#define I8TYPE(op,opsub,ry,r32) ( ((op)<<11) | ((opsub)<<8) | ((ry)<<5) | (r32))

#define I8MASK(opsub,ry,r32)    I8TYPE(0xc,opsub,ry,r32)

#define SFTTYPE(op,rx,ry,sm,f) \
	( ((op) << 11) | ((rx) << 8) | ((ry) << 5) | ((sm) << 2) | f)

#define SFTMASK(rx,ry,sm,f) SFTTYPE(0x6,rx,ry,sm,f)

char rx_ry[]      = "rx,ry";
char ra_rx[]      = "ra,rx";
char rr[]         = "rr";
char ry_rx[]      = "ry,rx";
char rx_ry_rz[]   = "rx,ry,rz";
char rz_rx_ry[]   = "rz,rx,ry";
char rx_i8[]      = "rx,i2";
char rx_ry_i5[]   = "rx,ry,i1";
char ry_rx_i4[] = "ry,rx,i0";
char f_i8[]       = "i2";
char rx_ry_sm[] = "rx,ry,im";
char ry_rm[]      = "ry,rm";
char ro_rn[]      = "ro,rn";
char ry_m[]       = "ry,m";

char rx[]       = "rx";
char rx_b[]     = "rx,b";
char i4[]       = "i0";
char i5[]       = "i1";
char i8[]       = "i2";
char ix[]       = "ix";

/* end mips16 */

/* Standard VxWorks tokens */

#define LOCAL static

/* globals */

/* strings describing operand formats */
LOCAL char B[] = "B";		/* break code */
LOCAL char C_m[] = "C,m";	/* Bits20:16,immediate_offset(GPR_base)
				 * Bits 20:16 are "op" for CACHE instruction
				 * and hint for PREF instruction 
   				 */
LOCAL char H[] = "H";           /* Hint field of PREFX instruction */
LOCAL char d[] = "d";		/* "cc" (condition code)field in instructions that read from it */
LOCAL char w[] = "w";		/* "cc" field in instructions that write into it */
LOCAL char m[] = "m";		/* immediate_offset(GPR_base) */
LOCAL char n[] = "n";		/* GPR_index(GPR_base).  rs(rt) */
LOCAL char S[] = "S";		/* syscall */
LOCAL char b[] = "b";		/* 16 bit branch offset */
LOCAL char d_b[]  ="d,b";