📄 lpc177x_8x_emc.c
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LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 1:
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 2:
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P2( add_mapped_p2);
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 3:
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Enable/disable the buffer
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] buff_control buffer control mode, should be:
*
* - EMC_DYNAMIC_CFG_BUFF_DISABLED: buffer is disabled
*
* - EMC_DYNAMIC_CFG_BUFF_ENABLED: buffer is enable
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
{
switch ( index)
{
case 0:
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
LPC_EMC->DynamicConfig0 |= buff_control & EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
break;
case 1:
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
LPC_EMC->DynamicConfig1 |= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
break;
case 2:
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
LPC_EMC->DynamicConfig2 |= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
break;
case 3:
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
LPC_EMC->DynamicConfig3|= buff_control& EMC_DYNAMIC_CFG_BUFFENABLE_BMASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure write permission: protect or not
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] permission permission mode, should be:
*
* - EMC_DYNAMIC_CFG_WR_UNPROTECTED: will not protect
*
* - EMC_DYNAMIC_CFG_WR_PROTECTED: will protect
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemConfigP(uint32_t index , uint32_t permission)
{
switch ( index)
{
case 0:
LPC_EMC->DynamicConfig0 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
LPC_EMC->DynamicConfig0 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
break;
case 1:
LPC_EMC->DynamicConfig1 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
LPC_EMC->DynamicConfig1 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
break;
case 2:
LPC_EMC->DynamicConfig2 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
LPC_EMC->DynamicConfig2 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
break;
case 3:
LPC_EMC->DynamicConfig3 &= ~ EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
LPC_EMC->DynamicConfig3 |= permission&EMC_DYNAMIC_CFG_WRPROTECT_BMASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Set value for RAS latency
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] ras_val RAS value should be in range: 0..3
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
{
switch ( index)
{
case 0:
LPC_EMC->DynamicRasCas0 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
LPC_EMC->DynamicRasCas0 |=( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS)
&EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
break;
case 1:
LPC_EMC->DynamicRasCas1 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
LPC_EMC->DynamicRasCas1 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS)
&EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
break;
case 2:
LPC_EMC->DynamicRasCas2 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
LPC_EMC->DynamicRasCas2 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS)
&EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
break;
case 3:
LPC_EMC->DynamicRasCas3 &= ~EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
LPC_EMC->DynamicRasCas3 |= ( ras_val << EMC_DYNAMIC_RASCAS_RASCFG_POS)
&EMC_DYNAMIC_RASCAS_RASCFG_BMASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Set value for CAS latency
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] ras_val CAS value should be in range: 0..3
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
{
switch ( index)
{
case 0:
LPC_EMC->DynamicRasCas0 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
LPC_EMC->DynamicRasCas0 |= (cas_val<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
&EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
break;
case 1:
LPC_EMC->DynamicRasCas1 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
LPC_EMC->DynamicRasCas1 |= (cas_val<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
&EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
break;
case 2:
LPC_EMC->DynamicRasCas2 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
LPC_EMC->DynamicRasCas2 |= (cas_val<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
&EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
break;
case 3:
LPC_EMC->DynamicRasCas3 &= ~EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
LPC_EMC->DynamicRasCas3 |= (cas_val<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
&EMC_DYNAMIC_RASCAS_CASCFG_BMASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Set extended wait time out for accessing static memory
*
* @param[in] Extended_wait_time_out timeout value that will be set
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
{
LPC_EMC->StaticExtendedWait = EMC_StaticExtendedWait_EXTENDEDWAIT(Extended_wait_time_out);
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure the memory width
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] mem_width memory width, should be:
*
* - EMC_STATIC_CFG_MW_8BITS: 8-bits
*
* - EMC_STATIC_CFG_MW_16BITS: 16-bits
*
* - EMC_STATIC_CFG_MW_32BITS02: 32-bits
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
{
uint32_t mem_width_flg = 0;
switch(mem_width)
{
case 8:
mem_width_flg = EMC_STATIC_CFG_MW_8BITS;
break;
case 16:
mem_width_flg = EMC_STATIC_CFG_MW_16BITS;
break;
case 32:
mem_width_flg = EMC_STATIC_CFG_MW_32BITS;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
switch ( index)
{
case 0:
LPC_EMC->StaticConfig0 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK;
LPC_EMC->StaticConfig0 |= mem_width_flg;
break;
case 1:
LPC_EMC->StaticConfig1 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK;
LPC_EMC->StaticConfig1 |= mem_width_flg;
break;
case 2:
LPC_EMC->StaticConfig2 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK;
LPC_EMC->StaticConfig2 |= mem_width_flg;
break;
case 3:
LPC_EMC->StaticConfig3 &= ~ EMC_STATIC_CFG_MEMWIDTH_BMASK;
LPC_EMC->StaticConfig3 |= mem_width_flg;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure the page mode
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] page_mode page mode, should be:
*
* - EMC_CFG_PM_DISABLE: disable
*
* - EMC_CFG_PM_ASYNC_ENABLE: asynchronous page mode enable
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
{
switch ( index)
{
case 0:
LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_PAGEMODE_MASK;
LPC_EMC->StaticConfig0 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK;
break;
case 1:
LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_PAGEMODE_MASK;
LPC_EMC->StaticConfig1 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK;
break;
case 2:
LPC_EMC->StaticConfig2 &= ~EMC_STATIC_CFG_PAGEMODE_MASK;
LPC_EMC->StaticConfig2 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK;
break;
case 3:
LPC_EMC->StaticConfig3 &= ~EMC_STATIC_CFG_PAGEMODE_MASK;
LPC_EMC->StaticConfig3 |= page_mode&EMC_STATIC_CFG_PAGEMODE_MASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure the chip select polarity
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] pagepol_val_mode page mode, should be:
*
* - EMC_CFG_BYTELAND_PC_ACTIVE_LO: Active LOW ship select
*
* - EMC_CFG_BYTELAND_PC_ACTIVE_HI: Active HIGH chip select
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
{
switch ( index)
{
case 0:
LPC_EMC->StaticConfig0 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK;
LPC_EMC->StaticConfig0 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK;
break;
case 1:
LPC_EMC->StaticConfig1 &= ~EMC_STATIC_CFG_CHIPPOLARITY_MASK;
LPC_EMC->StaticConfig1 |= pol_val&EMC_STATIC_CFG_CHIPPOLARITY_MASK;
break;
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