📄 lpc177x_8x_emc.c
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PINSEL_ConfigPin(5,0,1);
PINSEL_ConfigPin(5,1,1);
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure Little Endian/Big Endian mode for EMC
*
* @param[in] endia_mode Endian mode, should be:
*
* - EMC_Config_Little_Endian_Mode: Little-endian mode
*
* - EMC_Config_Big_Endian_Mode : Big-endian mode
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_ConfigEndianMode(uint32_t endian_mode)
{
LPC_EMC->Config &= ~(EMC_Config_Endian_Mask);
LPC_EMC->Config |= (endian_mode&EMC_Config_Endian_Mask);
return EMC_FUNC_OK;
}
/****************** Group of Dynamic control functions************************/
/*********************************************************************//**
* @brief Set the dsvalue for dynamic clock enable bit
*
* @param[in] clock_enable clock enable mode, should be:
*
* - EMC_DYNAMIC_CTRL_CE_SAVEPWR: Clock enable of idle devices
* are deasserted to save power
*
* - EMC_DYNAMIC_CTRL_CE_ALLCLK_HI: All clock enables are driven
* HIGH continuously
*
* @return EMC_FUNC_CODE
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlClockEnable(uint32_t clock_enable)
{
LPC_EMC->DynamicControl &= ~(EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK);
LPC_EMC->DynamicControl |= clock_enable & EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Set the value for dynamic memory clock control: stops or
* runs continuously
*
* @param[in] clock_control clock control mode, should be:
*
* - EMC_DYNAMIC_CTRL_CS_CLKOUT_STOP: CLKOUT stops when all
* SDRAMs are idle and during self-refresh mode
*
* - EMC_DYNAMIC_CTRL_CS_CLKOUT_CONT: CLKOUT runs continuously
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlClockControl(int32_t clock_control)
{
LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_CLKCTRL_BMASK;
LPC_EMC->DynamicControl |= clock_control & EMC_DYNAMIC_CTRL_CLKCTRL_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Switch the Self-refresh mode between normal and self-refresh mode
*
* @param[in] self_refresh_mode self refresh mode, should be:
*
* - EMC_DYNAMIC_CTRL_SR_NORMALMODE: Normal mode
*
* - EMC_DYNAMIC_CTRL_SR_SELFREFRESH: Enter self-refresh mode
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
{
LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK;
LPC_EMC->DynamicControl =self_refresh_mode & EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Enable/disable CLKOUT
*
* @param[in] MMC_val Memory clock control mode, should be:
*
* - EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED: CLKOUT enabled
*
* - EMC_DYNAMIC_CTRL_MMC_CLKOUT_DISABLED: CLKOUT disabled
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlMMC(uint32_t MMC_val)
{
LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK;
LPC_EMC->DynamicControl |=MMC_val & EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Issue SDRAM command
*
* @param[in] SDRAM_command Command mode, should be:
*
* - EMC_DYNAMIC_CTRL_SDRAM_NORMAL: Issue SDRAM NORMAL operation command
*
* - EMC_DYNAMIC_CTRL_SDRAM_MODE: Issue SDRAM MODE command
*
* - EMC_DYNAMIC_CTRL_SDRAM_PALL: Issue SDRAM PALL (precharge all) command
*
* - EMC_DYNAMIC_CTRL_SDRAM_NOP: Issue SRAM NOP (no operation) command
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
{
LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK;
LPC_EMC->DynamicControl |= SDRAM_command & EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Switch between Normal operation and deep sleep power mode
*
* @param[in] Power_command Low-power SDRAM deep-sleep mode, should be:
*
* - EMC_DYNAMIC_CTRL_DP_NORMAL: Normal operation
*
* - EMC_DYNAMIC_CTRL_DP_DEEPSLEEP: Enter deep-sleep mode
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynCtrlPowerDownMode(uint32_t Power_command)
{
LPC_EMC->DynamicControl &= ~EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK;
LPC_EMC->DynamicControl |= Power_command & EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK;
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Set the value of EMC dynamic memory registers
*
* @param[in] par EMC register that will set value, should be:
* - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
* - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
* - EMC_DYN_MEM_TRP: Dynamic RP register
* - EMC_DYN_MEM_TRAS: Dynamic RAS register
* - EMC_DYN_MEM_TSREX: Dynamic SREX register
* - EMC_DYN_MEM_TAPR: Dynamic APR register
* - EMC_DYN_MEM_TDAL: Dynamic DAL register
* - EMC_DYN_MEM_TWR: Dynamic WR register
* - EMC_DYN_MEM_TRC: Dynamic RC register
* - EMC_DYN_MEM_TRFC: Dynamic RFC register
* - EMC_DYN_MEM_TXSR: Dynamic XSR register
* - EMC_DYN_MEM_TRRD: Dynamic RRD register
* - EMC_DYN_MEM_TMRD: Dynamic MRD register
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
{
switch ( par)
{
case EMC_DYN_MEM_REFRESH_TIMER:
LPC_EMC->DynamicRefresh = EMC_DynamicRefresh_REFRESH(val);
break;
case EMC_DYN_MEM_READ_CONFIG:
LPC_EMC->DynamicReadConfig = EMC_DynamicReadConfig_RD(val);
break;
case EMC_DYN_MEM_TRP:
LPC_EMC->DynamicRP = EMC_DynamictRP_tRP(val);
break;
case EMC_DYN_MEM_TRAS:
LPC_EMC->DynamicRAS = EMC_DynamictRP_tRAS(val);
break;
case EMC_DYN_MEM_TSREX:
LPC_EMC->DynamicSREX = EMC_DynamictRP_tSREX(val);
break;
case EMC_DYN_MEM_TAPR:
LPC_EMC->DynamicAPR = EMC_DynamictAPR_tAPR(val);
break;
case EMC_DYN_MEM_TDAL:
LPC_EMC->DynamicDAL =EMC_DynamictDAL_tDAL(val);
break;
case EMC_DYN_MEM_TWR:
LPC_EMC->DynamicWR = EMC_DynamictWR_tWR(val);
break;
case EMC_DYN_MEM_TRC:
LPC_EMC->DynamicRC = EMC_DynamictRC_tRC(val);
break;
case EMC_DYN_MEM_TRFC:
LPC_EMC->DynamicRFC = EMC_DynamictRFC_tRFC(val);
break;
case EMC_DYN_MEM_TXSR:
LPC_EMC->DynamicXSR = EMC_DynamictXSR_tXSR(val);
break;
case EMC_DYN_MEM_TRRD:
LPC_EMC->DynamicRRD = EMC_DynamictRRD_tRRD(val);
break;
case EMC_DYN_MEM_TMRD:
LPC_EMC->DynamicMRD = EMC_DynamictMRD_tMRD(val);
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Configure the memory device
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] mem_dev Memory device, should be:
*
* - EMC_DYNAMIC_CFG_MEMDEV_SDRAM: SDRAM
*
* - EMC_DYNAMIC_CFG_MEMDEV_LOWPWR_SDRAM: Low-power SDRAM
*
*
* @return EMC_FUNC_OK/EMC_FUNC_INVALID_PARAM
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
{
switch (index)
{
case 0:
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK;
LPC_EMC->DynamicConfig0 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK;
break;
case 1:
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK;
LPC_EMC->DynamicConfig1 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK;
break;
case 2:
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK;
LPC_EMC->DynamicConfig2 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK;
break;
case 3:
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_MEMDEV_BMASK;
LPC_EMC->DynamicConfig3 |= mem_dev & EMC_DYNAMIC_CFG_MEMDEV_BMASK;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}
/*********************************************************************//**
* @brief Map the address for the memory device
*
* @param[in] index index number, should be from 0 to 3
*
* @param[in] add_mapped address where the memory will be mapped
*
* @return EMC_FUNC_OK
**********************************************************************/
EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index ,
uint8_t addr_bus_width, uint8_t addr_map,
uint8_t data_bus_width,
uint16_t chip_size)
{
const int chip_max_size = 512; // 512Mb
uint8_t data_bus_max_size = 0;
uint32_t add_mapped_p1 = 0x00, add_mapped_p2 = 0x00, add_mapped_p3 = 0x00;
uint32_t tmp = 16, i = 0, j = 0;
/* Get part 3 of address map */
switch(addr_bus_width)
{
case 16:
add_mapped_p3 = 0;
data_bus_max_size = 16;
break;
case 32:
add_mapped_p3 = 1;
data_bus_max_size = 32;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
/* Get part 2 of address map */
add_mapped_p2 = EMC_DYNAMIC_CFG_ADD_MAP_P2(addr_map);
/* Get part 1 of address map */
if(chip_size == 16)
{
if(data_bus_width == 8)
add_mapped_p1 = 0;
else if(data_bus_width == 16)
add_mapped_p1 = 1;
else
return EMC_FUNC_INVALID_PARAM;
}
else
{
while(1)
{
i++;
tmp = 16*(0x01 << (i+1));
if(tmp == chip_size)
{
for(j = 0; (8<<j)<=data_bus_max_size;j++)
{
if((8<<j) == data_bus_width)
break;
}
if( (8<<j) > data_bus_max_size)
return EMC_FUNC_INVALID_PARAM;
add_mapped_p1 = (i<<2) + j;
break;
}
if(tmp >= chip_max_size)
{
return EMC_FUNC_INVALID_PARAM;
}
}
}
switch ( index)
{
case 0:
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
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