lpc177x_8x_emc.h

NXPl788上lwip的无操作系统移植,基于Embest开发板

#define EMC_DYNAMIC_RASCAS_RASLATENCY_RESVD		(0<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_1CLK		(1<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_2CLK		(2<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
#define EMC_DYNAMIC_RASCAS_RASLATENCY_3CLK		(3<<EMC_DYNAMIC_RASCAS_RASCFG_POS)


/* DynamicRASCAS register EMC: CAS latency (CAS)*/
#define EMC_DYNAMIC_RASCAS_CASCFG_POS			(8)
#define EMC_DYNAMIC_RASCAS_CASCFG_BMASK			(0x03<<EMC_DYNAMIC_RASCAS_CASCFG_POS)

#define EMC_DYNAMIC_RASCAS_CASLATENCY_RESVD		(0<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_1CLK		(1<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_2CLK		(2<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
#define EMC_DYNAMIC_RASCAS_CASLATENCY_3CLK		(3<<EMC_DYNAMIC_RASCAS_CASCFG_POS)

/***********************************************************************
 * Static Memory Configuration registers (EMCStaticConfig0-3)
 **********************************************************************/
/* StaticConfig register EMC: Memory width (MW). */
#define EMC_STATIC_CFG_MEMWIDTH_POS		(0)
#define EMC_STATIC_CFG_MEMWIDTH_BMASK		(0x03<<EMC_STATIC_CFG_MEMWIDTH_POS)
#define EMC_StaticConfig_MW(n)			((uint32_t )((n<<EMC_STATIC_CFG_MEMWIDTH_POS) & EMC_STATIC_CFG_MEMWIDTH_BMASK))

/* StaticConfig register EMC: Memory width 8bit . */
#define EMC_STATIC_CFG_MW_8BITS			(EMC_StaticConfig_MW(0))

/* StaticConfig register EMC: Memory width 16bit . */
#define EMC_STATIC_CFG_MW_16BITS		(EMC_StaticConfig_MW(1))

/* StaticConfig register EMC: Memory width 32bit . */
#define EMC_STATIC_CFG_MW_32BITS		(EMC_StaticConfig_MW(2))

/* StaticConfig register EMC: Page mode (PM) */
#define EMC_STATIC_CFG_PAGEMODE_POS				(3)
#define EMC_STATIC_CFG_PAGEMODE_MASK				(1<<EMC_STATIC_CFG_PAGEMODE_POS)

#define EMC_CFG_PM_DISABLE					(0<<EMC_STATIC_CFG_PAGEMODE_POS)
#define EMC_CFG_PM_ASYNC_ENABLE					(1<<EMC_STATIC_CFG_PAGEMODE_POS)


/* StaticConfig register EMC: Chip select polarity (PC) */
#define EMC_STATIC_CFG_CHIPPOLARITY_POS			(6)
#define EMC_STATIC_CFG_CHIPPOLARITY_MASK			(1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)

#define EMC_CFG_BYTELAND_PC_ACTIVE_LO				(0<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
#define EMC_CFG_BYTELAND_PC_ACTIVE_HI				(1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)


/* StaticConfig register EMC: Byte lane state (PB) */
#define EMC_STATIC_CFG_BYTELAND_POS				(7)
#define EMC_STATIC_CFG_BYTELAND_MASK				(1<<EMC_STATIC_CFG_BYTELAND_POS)

#define EMC_CFG_BYTELAND_READ_BITSHIGH				(0<<EMC_STATIC_CFG_BYTELAND_POS)
#define EMC_CFG_BYTELAND_READ_BITSLOW				(1<<EMC_STATIC_CFG_BYTELAND_POS)


/* StaticConfig register EMC: Extended wait (EW) */
#define EMC_STATIC_CFG_EXTWAIT_POS				(8)
#define EMC_STATIC_CFG_EXTWAIT_MASK				(1<<EMC_STATIC_CFG_EXTWAIT_POS)

#define EMC_CFG_EW_DISABLED					(0<<EMC_STATIC_CFG_EXTWAIT_POS)
#define EMC_CFG_EW_ENABLED					(1<<EMC_STATIC_CFG_EXTWAIT_POS)


/* StaticConfig register EMC: Buffer enable (B) */
#define EMC_STATIC_CFG_BUFENABLE_POS				(19)
#define EMC_STATIC_CFG_BUFENABLE_MASK				(1<<EMC_STATIC_CFG_BUFENABLE_POS)

#define EMC_CFG_BUF_DISABLED					(0<<EMC_STATIC_CFG_BUFENABLE_POS)
#define EMC_CFG_BUF_ENABLED					(1<<EMC_STATIC_CFG_BUFENABLE_POS)

/* StaticConfig register EMC: Write protect (P) */
#define EMC_STATIC_CFG_WRIEPROTECT_POS				(20)
#define EMC_STATIC_CFG_WRIEPROTECT_MASK				(1<<EMC_STATIC_CFG_WRIEPROTECT_POS)

#define EMC_CFG_WRITEPROTECT_DISABLED				(0<<EMC_STATIC_CFG_WRIEPROTECT_POS)
#define EMC_CFG_WRITEPROTECT_ENABLED				(1<<EMC_STATIC_CFG_WRIEPROTECT_POS)

/***********************************************************************
 * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
 **********************************************************************/
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
#define EMC_StaticWaitWen_WAITWEN(n)	((uint32_t )(n & 0x0f))

/***********************************************************************
 * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
 **********************************************************************/
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
#define EMC_StaticWaitOen_WAITOEN(n)	((uint32_t )(n & 0x0f))

/***********************************************************************
 * Static Memory Read Delay registers (EMCStaticWaitRd0-3)
 **********************************************************************/
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
read first access wait state (WAITRD) */
#define EMC_StaticWaitRd_WAITRD(n)		((uint32_t )(n & 0x1f))

/***********************************************************************
 * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
 **********************************************************************/
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
read wait states (WAITPAGE). */
#define EMC_StaticwaitPage_WAITPAGE(n)	((uint32_t )(n & 0x1f))

/***********************************************************************
 * Static Memory Write Delay registers (EMCStaticWaitwr0-3)
 **********************************************************************/
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
#define EMC_StaticWaitwr_WAITWR(n)		((uint32_t )(n & 0x1f))

/***********************************************************************
 * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
 **********************************************************************/
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
#define EMC_StaticWaitTurn_WAITTURN(n)	((uint32_t )(n & 0x0f))

/***********************************************************************
 * Delay Control register (EMCDLYCTL)
 **********************************************************************/
#define EMC_DLYCTL_CMDDLY(n)		((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n)		((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n)	((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n)	((uint32_t)((n&0x1F)<<24))

/***********************************************************************
 * EMC Calibration register (EMCCAL)
 **********************************************************************/
#define EMC_CAL_CALVALUE(n)			((uint32_t)(n&0xFF))
#define EMC_CAL_START				((uint32_t)(1<<14))
#define EMC_CAL_DONE				((uint32_t)(1<<15))

/***********************************************************************
 * EMC Function Return codes
 **********************************************************************/
 typedef int32_t EMC_FUNC_CODE;
#define  EMC_FUNC_OK                            (0)
#define  EMC_FUNC_ERR                           (0x01)
#define  EMC_FUNC_INVALID_PARAM                 (0x02)


/**
 * @}
 */


/* Public Types --------------------------------------------------------------- */
/** @defgroup EMC_Public_Types EMC Public Types
 * @{
 */
/*EMC dynamic memory registers enum*/
typedef enum
{
  EMC_DYN_MEM_REFRESH_TIMER,
  EMC_DYN_MEM_READ_CONFIG,
  EMC_DYN_MEM_TRP,
  EMC_DYN_MEM_TRAS,
  EMC_DYN_MEM_TSREX,
  EMC_DYN_MEM_TAPR,
  EMC_DYN_MEM_TDAL,
  EMC_DYN_MEM_TWR,
  EMC_DYN_MEM_TRC,
  EMC_DYN_MEM_TRFC,
  EMC_DYN_MEM_TXSR,
  EMC_DYN_MEM_TRRD,
  EMC_DYN_MEM_TMRD
} EMC_DYN_MEM_PAR;

/*EMC static memory registers enum*/
typedef enum
{
  EMC_STA_MEM_WAITWEN,
  EMC_STA_MEM_WAITOEN,
  EMC_STA_MEM_WAITRD,
  EMC_STA_MEM_WAITPAGE,
  EMC_STA_MEM_WAITWR,
  EMC_STA_MEM_WAITTURN,
} EMC_STA_MEM_PAR;

/* SDRAM Config Struct */
typedef struct
{
    uint8_t  CSn;         // 0/1/2/3
    uint32_t TotalSize;   // SDRAM TotalSize
    uint16_t ChipSize;    // chip size(Mb): 16Mb, 64Mb, 128Mb, 256Mb, 512Mb
    uint8_t   DataWidth;  // 8bit, 16 bit, 32bit
    uint8_t   AddrBusWidth;  // 16bit, 32bit
    uint8_t   AddrMap;           // EMC_ADD_MAP_BANK_ROW_COL/ EMC_ADD_MAP_ROW_BANK_COL

    /* timming */
    uint16_t RefreshTime;  // Dynamic Refresh Time
    uint8_t  ReadConfig;    // Read Config Strategy
    uint8_t  PrechargeCmdPeriod;  // Precharge Command Period (tRP)
    uint8_t SeftRefreshExitTime; // Self-Refresh Exit Time (tSREX)
    uint8_t DataOut2ActiveTime;            // the last-data-out to active command time (tAPR)
    uint8_t DataIn2ActiveTime;      //  the data-in to active command time (tDAL, or tAPW)
    uint8_t WriteRecoveryTime;      // the write recovery time (tWR, tDPL, tRWL, or tRDL)
    uint8_t Active2ActivePeriod;       // the active to active command period (tRC)
    uint8_t AutoRefrehPeriod;      // the auto-refresh period and auto-refresh to active command period (tRFC/tRC)
    uint8_t ExitSelfRefreshTime; // the exit self-refresh to active command time (tXSR)
    uint8_t ActiveBankLatency;  // the active bank A to active bank B latency (tRRD)
    uint8_t LoadModeReg2Active;            // the load mode register to active command time (tMRD)
    uint8_t Active2PreChargeTime;     // Active to precharge command period (tRAS)
    uint8_t  RASLatency;          // RAS Delay
    uint8_t  CASLatency;          // CAS Delay
	
} EMC_DYN_MEM_Config_Type;

typedef struct
{
    uint8_t  CSn;         // 0/1/2/3
    uint8_t DataWidth;    // 8bit, 16bit, 32bit
    uint8_t PageMode;   // 1: asynchronous page mode enabled
    uint8_t ByteLane;   // 1: Read when active bits are low, 0: read when acrive bits are High
    uint8_t ExtendedWait;  //1: enabled
    uint8_t AddressMirror; // 1: reset memory map, 0: normal memory map

    uint8_t  WaitWEn;		// Delay from the chip select to the write enable (CCLK cycles) 
    uint8_t  WaitOEn;		// Delay from the chip select or address change to output enable (CCLK cycles)
    uint8_t  WaitRd;		// Delay from the chip select to the read access (CCLK cycles)
    uint8_t  WaitPage;		// Delay for asynchronous page mode sequential accesses (CCLK cycles)
    uint8_t  WaitWr;		// Delay from the chip select to the write access (CCLK cycles)
    uint8_t  WaitTurn;		// The number of bus turnaround cycles
} EMC_STATIC_MEM_Config_Type;
/**
 * @}
 */


/* Public Functions ----------------------------------------------------------- */
/** @defgroup EMC_Public_Functions EMC Public Functions
 * @{
 */
 uint32_t EMC_SDRAM_REFRESH(uint32_t time);
 uint32_t EMC_NS2CLK(uint32_t time);
 EMC_FUNC_CODE DynMem_Init(EMC_DYN_MEM_Config_Type* pConfig);
 EMC_FUNC_CODE StaticMem_Init(EMC_STATIC_MEM_Config_Type* pConfig);
 EMC_FUNC_CODE EMC_Init(void);
 EMC_FUNC_CODE EMC_ConfigEndianMode(uint32_t endian_mode);
 EMC_FUNC_CODE EMC_DynCtrlClockEnable(uint32_t clock_enable);
 EMC_FUNC_CODE EMC_DynCtrlClockControl(int32_t clock_control);
 EMC_FUNC_CODE EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
 EMC_FUNC_CODE EMC_DynCtrlMMC(uint32_t MMC_val);
 EMC_FUNC_CODE EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
 EMC_FUNC_CODE EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
 EMC_FUNC_CODE EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
 EMC_FUNC_CODE EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
 EMC_FUNC_CODE EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
 EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index , uint8_t addr_bus_width, uint8_t addr_map,uint8_t data_bus_width,uint16_t chip_size);
 EMC_FUNC_CODE EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
 EMC_FUNC_CODE EMC_DynMemConfigP(uint32_t index , uint32_t permission);
 EMC_FUNC_CODE EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
 EMC_FUNC_CODE EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
 EMC_FUNC_CODE EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
 EMC_FUNC_CODE EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
 EMC_FUNC_CODE EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
 EMC_FUNC_CODE EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
 EMC_FUNC_CODE EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
 EMC_FUNC_CODE EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
 EMC_FUNC_CODE EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
 EMC_FUNC_CODE EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);

/**
 * @}
 */


#endif /* __LPC177X_8X_EMC_H_ */

/**
 * @}
 */